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Searched refs:REG_SUPC_INTENSET (Results 1 – 11 of 11) sorted by relevance

/hal_atmel-latest/asf/sam0/include/samc20/instance/
Dsupc.h36 #define REG_SUPC_INTENSET (0x40001804) /**< \brief (SUPC) Interrupt Enable Set */ macro
45 #define REG_SUPC_INTENSET (*(RwReg *)0x40001804UL) /**< \brief (SUPC) Interrupt Enable Se… macro
/hal_atmel-latest/asf/sam0/include/samc21/instance/
Dsupc.h36 #define REG_SUPC_INTENSET (0x40001804) /**< \brief (SUPC) Interrupt Enable Set */ macro
45 #define REG_SUPC_INTENSET (*(RwReg *)0x40001804UL) /**< \brief (SUPC) Interrupt Enable Se… macro
/hal_atmel-latest/asf/sam0/include/samc20n/instance/
Dsupc.h36 #define REG_SUPC_INTENSET (0x40001804) /**< \brief (SUPC) Interrupt Enable Set */ macro
46 #define REG_SUPC_INTENSET (*(RwReg *)0x40001804UL) /**< \brief (SUPC) Interrupt Enable Se… macro
/hal_atmel-latest/asf/sam0/include/samc21n/instance/
Dsupc.h36 #define REG_SUPC_INTENSET (0x40001804) /**< \brief (SUPC) Interrupt Enable Set */ macro
46 #define REG_SUPC_INTENSET (*(RwReg *)0x40001804UL) /**< \brief (SUPC) Interrupt Enable Se… macro
/hal_atmel-latest/asf/sam0/include/samd51/instance/
Dsupc.h36 #define REG_SUPC_INTENSET (0x40001804) /**< \brief (SUPC) Interrupt Enable Set */ macro
47 #define REG_SUPC_INTENSET (*(RwReg *)0x40001804UL) /**< \brief (SUPC) Interrupt Enable Se… macro
/hal_atmel-latest/asf/sam0/include/same51/instance/
Dsupc.h36 #define REG_SUPC_INTENSET (0x40001804) /**< \brief (SUPC) Interrupt Enable Set */ macro
47 #define REG_SUPC_INTENSET (*(RwReg *)0x40001804UL) /**< \brief (SUPC) Interrupt Enable Se… macro
/hal_atmel-latest/asf/sam0/include/same54/instance/
Dsupc.h36 #define REG_SUPC_INTENSET (0x40001804) /**< \brief (SUPC) Interrupt Enable Set */ macro
47 #define REG_SUPC_INTENSET (*(RwReg *)0x40001804UL) /**< \brief (SUPC) Interrupt Enable Se… macro
/hal_atmel-latest/asf/sam0/include/same53/instance/
Dsupc.h36 #define REG_SUPC_INTENSET (0x40001804) /**< \brief (SUPC) Interrupt Enable Set */ macro
47 #define REG_SUPC_INTENSET (*(RwReg *)0x40001804UL) /**< \brief (SUPC) Interrupt Enable Se… macro
/hal_atmel-latest/asf/sam0/include/samr34/instance/
Dsupc.h36 #define REG_SUPC_INTENSET (0x40001404) /**< \brief (SUPC) Interrupt Enable Set */ macro
48 #define REG_SUPC_INTENSET (*(RwReg *)0x40001404UL) /**< \brief (SUPC) Interrupt Enable Se… macro
/hal_atmel-latest/asf/sam0/include/samr35/instance/
Dsupc.h36 #define REG_SUPC_INTENSET (0x40001404) /**< \brief (SUPC) Interrupt Enable Set */ macro
48 #define REG_SUPC_INTENSET (*(RwReg *)0x40001404UL) /**< \brief (SUPC) Interrupt Enable Se… macro
/hal_atmel-latest/asf/sam0/include/saml21/instance/
Dsupc.h36 #define REG_SUPC_INTENSET (0x40001404) /**< \brief (SUPC) Interrupt Enable Set */ macro
48 #define REG_SUPC_INTENSET (*(RwReg *)0x40001404UL) /**< \brief (SUPC) Interrupt Enable Se… macro