1 /** 2 * \file 3 * 4 * \brief Instance description for SUPC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMD51_SUPC_INSTANCE_ 31 #define _SAMD51_SUPC_INSTANCE_ 32 33 /* ========== Register definition for SUPC peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_SUPC_INTENCLR (0x40001800) /**< \brief (SUPC) Interrupt Enable Clear */ 36 #define REG_SUPC_INTENSET (0x40001804) /**< \brief (SUPC) Interrupt Enable Set */ 37 #define REG_SUPC_INTFLAG (0x40001808) /**< \brief (SUPC) Interrupt Flag Status and Clear */ 38 #define REG_SUPC_STATUS (0x4000180C) /**< \brief (SUPC) Power and Clocks Status */ 39 #define REG_SUPC_BOD33 (0x40001810) /**< \brief (SUPC) BOD33 Control */ 40 #define REG_SUPC_VREG (0x40001818) /**< \brief (SUPC) VREG Control */ 41 #define REG_SUPC_VREF (0x4000181C) /**< \brief (SUPC) VREF Control */ 42 #define REG_SUPC_BBPS (0x40001820) /**< \brief (SUPC) Battery Backup Power Switch */ 43 #define REG_SUPC_BKOUT (0x40001824) /**< \brief (SUPC) Backup Output Control */ 44 #define REG_SUPC_BKIN (0x40001828) /**< \brief (SUPC) Backup Input Control */ 45 #else 46 #define REG_SUPC_INTENCLR (*(RwReg *)0x40001800UL) /**< \brief (SUPC) Interrupt Enable Clear */ 47 #define REG_SUPC_INTENSET (*(RwReg *)0x40001804UL) /**< \brief (SUPC) Interrupt Enable Set */ 48 #define REG_SUPC_INTFLAG (*(RwReg *)0x40001808UL) /**< \brief (SUPC) Interrupt Flag Status and Clear */ 49 #define REG_SUPC_STATUS (*(RoReg *)0x4000180CUL) /**< \brief (SUPC) Power and Clocks Status */ 50 #define REG_SUPC_BOD33 (*(RwReg *)0x40001810UL) /**< \brief (SUPC) BOD33 Control */ 51 #define REG_SUPC_VREG (*(RwReg *)0x40001818UL) /**< \brief (SUPC) VREG Control */ 52 #define REG_SUPC_VREF (*(RwReg *)0x4000181CUL) /**< \brief (SUPC) VREF Control */ 53 #define REG_SUPC_BBPS (*(RwReg *)0x40001820UL) /**< \brief (SUPC) Battery Backup Power Switch */ 54 #define REG_SUPC_BKOUT (*(RwReg *)0x40001824UL) /**< \brief (SUPC) Backup Output Control */ 55 #define REG_SUPC_BKIN (*(RoReg *)0x40001828UL) /**< \brief (SUPC) Backup Input Control */ 56 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 57 58 /* ========== Instance parameters for SUPC peripheral ========== */ 59 #define SUPC_BOD12_CALIB_MSB 5 60 #define SUPC_BOD33_CALIB_MSB 5 61 62 #endif /* _SAMD51_SUPC_INSTANCE_ */ 63
