1 /** 2 * \file 3 * 4 * \brief Instance description for SUPC 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC20_SUPC_INSTANCE_ 31 #define _SAMC20_SUPC_INSTANCE_ 32 33 /* ========== Register definition for SUPC peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_SUPC_INTENCLR (0x40001800) /**< \brief (SUPC) Interrupt Enable Clear */ 36 #define REG_SUPC_INTENSET (0x40001804) /**< \brief (SUPC) Interrupt Enable Set */ 37 #define REG_SUPC_INTFLAG (0x40001808) /**< \brief (SUPC) Interrupt Flag Status and Clear */ 38 #define REG_SUPC_STATUS (0x4000180C) /**< \brief (SUPC) Power and Clocks Status */ 39 #define REG_SUPC_BODVDD (0x40001810) /**< \brief (SUPC) BODVDD Control */ 40 #define REG_SUPC_BODCORE (0x40001814) /**< \brief (SUPC) BODCORE Control */ 41 #define REG_SUPC_VREG (0x40001818) /**< \brief (SUPC) VREG Control */ 42 #define REG_SUPC_VREF (0x4000181C) /**< \brief (SUPC) VREF Control */ 43 #define REG_SUPC_VREG33 (0x40001820) /**< \brief (SUPC) VREG33 Control */ 44 #else 45 #define REG_SUPC_INTENCLR (*(RwReg *)0x40001800UL) /**< \brief (SUPC) Interrupt Enable Clear */ 46 #define REG_SUPC_INTENSET (*(RwReg *)0x40001804UL) /**< \brief (SUPC) Interrupt Enable Set */ 47 #define REG_SUPC_INTFLAG (*(RwReg *)0x40001808UL) /**< \brief (SUPC) Interrupt Flag Status and Clear */ 48 #define REG_SUPC_STATUS (*(RoReg *)0x4000180CUL) /**< \brief (SUPC) Power and Clocks Status */ 49 #define REG_SUPC_BODVDD (*(RwReg *)0x40001810UL) /**< \brief (SUPC) BODVDD Control */ 50 #define REG_SUPC_BODCORE (*(RwReg *)0x40001814UL) /**< \brief (SUPC) BODCORE Control */ 51 #define REG_SUPC_VREG (*(RwReg *)0x40001818UL) /**< \brief (SUPC) VREG Control */ 52 #define REG_SUPC_VREF (*(RwReg *)0x4000181CUL) /**< \brief (SUPC) VREF Control */ 53 #define REG_SUPC_VREG33 (*(RwReg *)0x40001820UL) /**< \brief (SUPC) VREG33 Control */ 54 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 55 56 /* ========== Instance parameters for SUPC peripheral ========== */ 57 #define SUPC_BODCORE_CALIB_MSB 5 58 #define SUPC_BODVDD_CALIB_MSB 5 59 #define SUPC_SUPC_OUT_NUM_MSB 1 // MSB of backup output pad Number 60 61 #endif /* _SAMC20_SUPC_INSTANCE_ */ 62
