Searched refs:REG_AFEC0_IMR (Results 1 – 5 of 5) sorted by relevance
46 #define REG_AFEC0_IMR (0x400B002CU) /**< \brief (AFEC0) Interrupt Mask Register */ macro79 #define REG_AFEC0_IMR (*(RoReg*)0x400B002CU) /**< \brief (AFEC0) Interrupt Mask Register */ macro
48 #define REG_AFEC0_IMR (0x4003C02C) /**< (AFEC0) AFEC Interrupt Mask Register */ macro81 #define REG_AFEC0_IMR (*(__I uint32_t*)0x4003C02CU) /**< (AFEC0) AFEC Interrupt Mask Reg… macro
48 #define REG_AFEC0_IMR (0x4003C02C) /**< (AFEC0) AFEC Interrupt Mask Register */ macro80 #define REG_AFEC0_IMR (*(__I uint32_t*)0x4003C02CU) /**< (AFEC0) AFEC Interrupt Mask Reg… macro
