1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM4E_AFEC0_INSTANCE_ 31 #define _SAM4E_AFEC0_INSTANCE_ 32 33 /* ========== Register definition for AFEC0 peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_AFEC0_CR (0x400B0000U) /**< \brief (AFEC0) Control Register */ 36 #define REG_AFEC0_MR (0x400B0004U) /**< \brief (AFEC0) Mode Register */ 37 #define REG_AFEC0_EMR (0x400B0008U) /**< \brief (AFEC0) Extended Mode Register */ 38 #define REG_AFEC0_SEQ1R (0x400B000CU) /**< \brief (AFEC0) Channel Sequence 1 Register */ 39 #define REG_AFEC0_SEQ2R (0x400B0010U) /**< \brief (AFEC0) Channel Sequence 2 Register */ 40 #define REG_AFEC0_CHER (0x400B0014U) /**< \brief (AFEC0) Channel Enable Register */ 41 #define REG_AFEC0_CHDR (0x400B0018U) /**< \brief (AFEC0) Channel Disable Register */ 42 #define REG_AFEC0_CHSR (0x400B001CU) /**< \brief (AFEC0) Channel Status Register */ 43 #define REG_AFEC0_LCDR (0x400B0020U) /**< \brief (AFEC0) Last Converted Data Register */ 44 #define REG_AFEC0_IER (0x400B0024U) /**< \brief (AFEC0) Interrupt Enable Register */ 45 #define REG_AFEC0_IDR (0x400B0028U) /**< \brief (AFEC0) Interrupt Disable Register */ 46 #define REG_AFEC0_IMR (0x400B002CU) /**< \brief (AFEC0) Interrupt Mask Register */ 47 #define REG_AFEC0_ISR (0x400B0030U) /**< \brief (AFEC0) Interrupt Status Register */ 48 #define REG_AFEC0_OVER (0x400B004CU) /**< \brief (AFEC0) Overrun Status Register */ 49 #define REG_AFEC0_CWR (0x400B0050U) /**< \brief (AFEC0) Compare Window Register */ 50 #define REG_AFEC0_CGR (0x400B0054U) /**< \brief (AFEC0) Channel Gain Register */ 51 #define REG_AFEC0_CDOR (0x400B005CU) /**< \brief (AFEC0) Channel DC Offset Register */ 52 #define REG_AFEC0_DIFFR (0x400B0060U) /**< \brief (AFEC0) Channel Differential Register */ 53 #define REG_AFEC0_CSELR (0x400B0064U) /**< \brief (AFEC0) Channel Register Selection */ 54 #define REG_AFEC0_CDR (0x400B0068U) /**< \brief (AFEC0) Channel Data Register */ 55 #define REG_AFEC0_COCR (0x400B006CU) /**< \brief (AFEC0) Channel Offset Compensation Register */ 56 #define REG_AFEC0_TEMPMR (0x400B0070U) /**< \brief (AFEC0) Temperature Sensor Mode Register */ 57 #define REG_AFEC0_TEMPCWR (0x400B0074U) /**< \brief (AFEC0) Temperature Compare Window Register */ 58 #define REG_AFEC0_ACR (0x400B0094U) /**< \brief (AFEC0) Analog Control Register */ 59 #define REG_AFEC0_WPMR (0x400B00E4U) /**< \brief (AFEC0) Write Protect Mode Register */ 60 #define REG_AFEC0_WPSR (0x400B00E8U) /**< \brief (AFEC0) Write Protect Status Register */ 61 #define REG_AFEC0_RPR (0x400B0100U) /**< \brief (AFEC0) Receive Pointer Register */ 62 #define REG_AFEC0_RCR (0x400B0104U) /**< \brief (AFEC0) Receive Counter Register */ 63 #define REG_AFEC0_RNPR (0x400B0110U) /**< \brief (AFEC0) Receive Next Pointer Register */ 64 #define REG_AFEC0_RNCR (0x400B0114U) /**< \brief (AFEC0) Receive Next Counter Register */ 65 #define REG_AFEC0_PTCR (0x400B0120U) /**< \brief (AFEC0) Transfer Control Register */ 66 #define REG_AFEC0_PTSR (0x400B0124U) /**< \brief (AFEC0) Transfer Status Register */ 67 #else 68 #define REG_AFEC0_CR (*(WoReg*)0x400B0000U) /**< \brief (AFEC0) Control Register */ 69 #define REG_AFEC0_MR (*(RwReg*)0x400B0004U) /**< \brief (AFEC0) Mode Register */ 70 #define REG_AFEC0_EMR (*(RwReg*)0x400B0008U) /**< \brief (AFEC0) Extended Mode Register */ 71 #define REG_AFEC0_SEQ1R (*(RwReg*)0x400B000CU) /**< \brief (AFEC0) Channel Sequence 1 Register */ 72 #define REG_AFEC0_SEQ2R (*(RwReg*)0x400B0010U) /**< \brief (AFEC0) Channel Sequence 2 Register */ 73 #define REG_AFEC0_CHER (*(WoReg*)0x400B0014U) /**< \brief (AFEC0) Channel Enable Register */ 74 #define REG_AFEC0_CHDR (*(WoReg*)0x400B0018U) /**< \brief (AFEC0) Channel Disable Register */ 75 #define REG_AFEC0_CHSR (*(RoReg*)0x400B001CU) /**< \brief (AFEC0) Channel Status Register */ 76 #define REG_AFEC0_LCDR (*(RoReg*)0x400B0020U) /**< \brief (AFEC0) Last Converted Data Register */ 77 #define REG_AFEC0_IER (*(WoReg*)0x400B0024U) /**< \brief (AFEC0) Interrupt Enable Register */ 78 #define REG_AFEC0_IDR (*(WoReg*)0x400B0028U) /**< \brief (AFEC0) Interrupt Disable Register */ 79 #define REG_AFEC0_IMR (*(RoReg*)0x400B002CU) /**< \brief (AFEC0) Interrupt Mask Register */ 80 #define REG_AFEC0_ISR (*(RoReg*)0x400B0030U) /**< \brief (AFEC0) Interrupt Status Register */ 81 #define REG_AFEC0_OVER (*(RoReg*)0x400B004CU) /**< \brief (AFEC0) Overrun Status Register */ 82 #define REG_AFEC0_CWR (*(RwReg*)0x400B0050U) /**< \brief (AFEC0) Compare Window Register */ 83 #define REG_AFEC0_CGR (*(RwReg*)0x400B0054U) /**< \brief (AFEC0) Channel Gain Register */ 84 #define REG_AFEC0_CDOR (*(RwReg*)0x400B005CU) /**< \brief (AFEC0) Channel DC Offset Register */ 85 #define REG_AFEC0_DIFFR (*(RwReg*)0x400B0060U) /**< \brief (AFEC0) Channel Differential Register */ 86 #define REG_AFEC0_CSELR (*(RoReg*)0x400B0064U) /**< \brief (AFEC0) Channel Register Selection */ 87 #define REG_AFEC0_CDR (*(RoReg*)0x400B0068U) /**< \brief (AFEC0) Channel Data Register */ 88 #define REG_AFEC0_COCR (*(RoReg*)0x400B006CU) /**< \brief (AFEC0) Channel Offset Compensation Register */ 89 #define REG_AFEC0_TEMPMR (*(RwReg*)0x400B0070U) /**< \brief (AFEC0) Temperature Sensor Mode Register */ 90 #define REG_AFEC0_TEMPCWR (*(RwReg*)0x400B0074U) /**< \brief (AFEC0) Temperature Compare Window Register */ 91 #define REG_AFEC0_ACR (*(RwReg*)0x400B0094U) /**< \brief (AFEC0) Analog Control Register */ 92 #define REG_AFEC0_WPMR (*(RwReg*)0x400B00E4U) /**< \brief (AFEC0) Write Protect Mode Register */ 93 #define REG_AFEC0_WPSR (*(RoReg*)0x400B00E8U) /**< \brief (AFEC0) Write Protect Status Register */ 94 #define REG_AFEC0_RPR (*(RwReg*)0x400B0100U) /**< \brief (AFEC0) Receive Pointer Register */ 95 #define REG_AFEC0_RCR (*(RwReg*)0x400B0104U) /**< \brief (AFEC0) Receive Counter Register */ 96 #define REG_AFEC0_RNPR (*(RwReg*)0x400B0110U) /**< \brief (AFEC0) Receive Next Pointer Register */ 97 #define REG_AFEC0_RNCR (*(RwReg*)0x400B0114U) /**< \brief (AFEC0) Receive Next Counter Register */ 98 #define REG_AFEC0_PTCR (*(WoReg*)0x400B0120U) /**< \brief (AFEC0) Transfer Control Register */ 99 #define REG_AFEC0_PTSR (*(RoReg*)0x400B0124U) /**< \brief (AFEC0) Transfer Status Register */ 100 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 101 102 #endif /* _SAM4E_AFEC0_INSTANCE_ */ 103
