1 /** 2 * \file 3 * 4 * \brief Instance description for AFEC0 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-01-08T14:00:00Z */ 31 #ifndef _SAMV71_AFEC0_INSTANCE_H_ 32 #define _SAMV71_AFEC0_INSTANCE_H_ 33 34 /* ========== Register definition for AFEC0 peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_AFEC0_CR (0x4003C000) /**< (AFEC0) AFEC Control Register */ 38 #define REG_AFEC0_MR (0x4003C004) /**< (AFEC0) AFEC Mode Register */ 39 #define REG_AFEC0_EMR (0x4003C008) /**< (AFEC0) AFEC Extended Mode Register */ 40 #define REG_AFEC0_SEQ1R (0x4003C00C) /**< (AFEC0) AFEC Channel Sequence 1 Register */ 41 #define REG_AFEC0_SEQ2R (0x4003C010) /**< (AFEC0) AFEC Channel Sequence 2 Register */ 42 #define REG_AFEC0_CHER (0x4003C014) /**< (AFEC0) AFEC Channel Enable Register */ 43 #define REG_AFEC0_CHDR (0x4003C018) /**< (AFEC0) AFEC Channel Disable Register */ 44 #define REG_AFEC0_CHSR (0x4003C01C) /**< (AFEC0) AFEC Channel Status Register */ 45 #define REG_AFEC0_LCDR (0x4003C020) /**< (AFEC0) AFEC Last Converted Data Register */ 46 #define REG_AFEC0_IER (0x4003C024) /**< (AFEC0) AFEC Interrupt Enable Register */ 47 #define REG_AFEC0_IDR (0x4003C028) /**< (AFEC0) AFEC Interrupt Disable Register */ 48 #define REG_AFEC0_IMR (0x4003C02C) /**< (AFEC0) AFEC Interrupt Mask Register */ 49 #define REG_AFEC0_ISR (0x4003C030) /**< (AFEC0) AFEC Interrupt Status Register */ 50 #define REG_AFEC0_OVER (0x4003C04C) /**< (AFEC0) AFEC Overrun Status Register */ 51 #define REG_AFEC0_CWR (0x4003C050) /**< (AFEC0) AFEC Compare Window Register */ 52 #define REG_AFEC0_CGR (0x4003C054) /**< (AFEC0) AFEC Channel Gain Register */ 53 #define REG_AFEC0_DIFFR (0x4003C060) /**< (AFEC0) AFEC Channel Differential Register */ 54 #define REG_AFEC0_CSELR (0x4003C064) /**< (AFEC0) AFEC Channel Selection Register */ 55 #define REG_AFEC0_CDR (0x4003C068) /**< (AFEC0) AFEC Channel Data Register */ 56 #define REG_AFEC0_COCR (0x4003C06C) /**< (AFEC0) AFEC Channel Offset Compensation Register */ 57 #define REG_AFEC0_TEMPMR (0x4003C070) /**< (AFEC0) AFEC Temperature Sensor Mode Register */ 58 #define REG_AFEC0_TEMPCWR (0x4003C074) /**< (AFEC0) AFEC Temperature Compare Window Register */ 59 #define REG_AFEC0_ACR (0x4003C094) /**< (AFEC0) AFEC Analog Control Register */ 60 #define REG_AFEC0_SHMR (0x4003C0A0) /**< (AFEC0) AFEC Sample & Hold Mode Register */ 61 #define REG_AFEC0_COSR (0x4003C0D0) /**< (AFEC0) AFEC Correction Select Register */ 62 #define REG_AFEC0_CVR (0x4003C0D4) /**< (AFEC0) AFEC Correction Values Register */ 63 #define REG_AFEC0_CECR (0x4003C0D8) /**< (AFEC0) AFEC Channel Error Correction Register */ 64 #define REG_AFEC0_WPMR (0x4003C0E4) /**< (AFEC0) AFEC Write Protection Mode Register */ 65 #define REG_AFEC0_WPSR (0x4003C0E8) /**< (AFEC0) AFEC Write Protection Status Register */ 66 #define REG_AFEC0_VERSION (0x4003C0FC) /**< (AFEC0) AFEC Version Register */ 67 68 #else 69 70 #define REG_AFEC0_CR (*(__O uint32_t*)0x4003C000U) /**< (AFEC0) AFEC Control Register */ 71 #define REG_AFEC0_MR (*(__IO uint32_t*)0x4003C004U) /**< (AFEC0) AFEC Mode Register */ 72 #define REG_AFEC0_EMR (*(__IO uint32_t*)0x4003C008U) /**< (AFEC0) AFEC Extended Mode Register */ 73 #define REG_AFEC0_SEQ1R (*(__IO uint32_t*)0x4003C00CU) /**< (AFEC0) AFEC Channel Sequence 1 Register */ 74 #define REG_AFEC0_SEQ2R (*(__IO uint32_t*)0x4003C010U) /**< (AFEC0) AFEC Channel Sequence 2 Register */ 75 #define REG_AFEC0_CHER (*(__O uint32_t*)0x4003C014U) /**< (AFEC0) AFEC Channel Enable Register */ 76 #define REG_AFEC0_CHDR (*(__O uint32_t*)0x4003C018U) /**< (AFEC0) AFEC Channel Disable Register */ 77 #define REG_AFEC0_CHSR (*(__I uint32_t*)0x4003C01CU) /**< (AFEC0) AFEC Channel Status Register */ 78 #define REG_AFEC0_LCDR (*(__I uint32_t*)0x4003C020U) /**< (AFEC0) AFEC Last Converted Data Register */ 79 #define REG_AFEC0_IER (*(__O uint32_t*)0x4003C024U) /**< (AFEC0) AFEC Interrupt Enable Register */ 80 #define REG_AFEC0_IDR (*(__O uint32_t*)0x4003C028U) /**< (AFEC0) AFEC Interrupt Disable Register */ 81 #define REG_AFEC0_IMR (*(__I uint32_t*)0x4003C02CU) /**< (AFEC0) AFEC Interrupt Mask Register */ 82 #define REG_AFEC0_ISR (*(__I uint32_t*)0x4003C030U) /**< (AFEC0) AFEC Interrupt Status Register */ 83 #define REG_AFEC0_OVER (*(__I uint32_t*)0x4003C04CU) /**< (AFEC0) AFEC Overrun Status Register */ 84 #define REG_AFEC0_CWR (*(__IO uint32_t*)0x4003C050U) /**< (AFEC0) AFEC Compare Window Register */ 85 #define REG_AFEC0_CGR (*(__IO uint32_t*)0x4003C054U) /**< (AFEC0) AFEC Channel Gain Register */ 86 #define REG_AFEC0_DIFFR (*(__IO uint32_t*)0x4003C060U) /**< (AFEC0) AFEC Channel Differential Register */ 87 #define REG_AFEC0_CSELR (*(__IO uint32_t*)0x4003C064U) /**< (AFEC0) AFEC Channel Selection Register */ 88 #define REG_AFEC0_CDR (*(__I uint32_t*)0x4003C068U) /**< (AFEC0) AFEC Channel Data Register */ 89 #define REG_AFEC0_COCR (*(__IO uint32_t*)0x4003C06CU) /**< (AFEC0) AFEC Channel Offset Compensation Register */ 90 #define REG_AFEC0_TEMPMR (*(__IO uint32_t*)0x4003C070U) /**< (AFEC0) AFEC Temperature Sensor Mode Register */ 91 #define REG_AFEC0_TEMPCWR (*(__IO uint32_t*)0x4003C074U) /**< (AFEC0) AFEC Temperature Compare Window Register */ 92 #define REG_AFEC0_ACR (*(__IO uint32_t*)0x4003C094U) /**< (AFEC0) AFEC Analog Control Register */ 93 #define REG_AFEC0_SHMR (*(__IO uint32_t*)0x4003C0A0U) /**< (AFEC0) AFEC Sample & Hold Mode Register */ 94 #define REG_AFEC0_COSR (*(__IO uint32_t*)0x4003C0D0U) /**< (AFEC0) AFEC Correction Select Register */ 95 #define REG_AFEC0_CVR (*(__IO uint32_t*)0x4003C0D4U) /**< (AFEC0) AFEC Correction Values Register */ 96 #define REG_AFEC0_CECR (*(__IO uint32_t*)0x4003C0D8U) /**< (AFEC0) AFEC Channel Error Correction Register */ 97 #define REG_AFEC0_WPMR (*(__IO uint32_t*)0x4003C0E4U) /**< (AFEC0) AFEC Write Protection Mode Register */ 98 #define REG_AFEC0_WPSR (*(__I uint32_t*)0x4003C0E8U) /**< (AFEC0) AFEC Write Protection Status Register */ 99 #define REG_AFEC0_VERSION (*(__I uint32_t*)0x4003C0FCU) /**< (AFEC0) AFEC Version Register */ 100 101 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 102 103 /* ========== Instance Parameter definitions for AFEC0 peripheral ========== */ 104 #define AFEC0_DMAC_ID_RX 35 105 #define AFEC0_INSTANCE_ID 29 106 107 #endif /* _SAMV71_AFEC0_INSTANCE_ */ 108
