Searched refs:REG_AFEC0_CHER (Results 1 – 5 of 5) sorted by relevance
40 #define REG_AFEC0_CHER (0x400B0014U) /**< \brief (AFEC0) Channel Enable Register */ macro73 #define REG_AFEC0_CHER (*(WoReg*)0x400B0014U) /**< \brief (AFEC0) Channel Enable Register */ macro
42 #define REG_AFEC0_CHER (0x4003C014) /**< (AFEC0) AFEC Channel Enable Register */ macro75 #define REG_AFEC0_CHER (*(__O uint32_t*)0x4003C014U) /**< (AFEC0) AFEC Channel Enable Reg… macro
42 #define REG_AFEC0_CHER (0x4003C014) /**< (AFEC0) AFEC Channel Enable Register */ macro74 #define REG_AFEC0_CHER (*(__O uint32_t*)0x4003C014U) /**< (AFEC0) AFEC Channel Enable Reg… macro
