Searched refs:REG_AFEC0_CHDR (Results 1 – 5 of 5) sorted by relevance
41 #define REG_AFEC0_CHDR (0x400B0018U) /**< \brief (AFEC0) Channel Disable Register */ macro74 #define REG_AFEC0_CHDR (*(WoReg*)0x400B0018U) /**< \brief (AFEC0) Channel Disable Register */ macro
43 #define REG_AFEC0_CHDR (0x4003C018) /**< (AFEC0) AFEC Channel Disable Register */ macro76 #define REG_AFEC0_CHDR (*(__O uint32_t*)0x4003C018U) /**< (AFEC0) AFEC Channel Disable Re… macro
43 #define REG_AFEC0_CHDR (0x4003C018) /**< (AFEC0) AFEC Channel Disable Register */ macro75 #define REG_AFEC0_CHDR (*(__O uint32_t*)0x4003C018U) /**< (AFEC0) AFEC Channel Disable Re… macro
