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Searched refs:REG_TC0_SR0 (Results 1 – 8 of 8) sorted by relevance

/hal_atmel-3.6.0/asf/sam/include/sam4l/instance/
Dtc0.h41 #define REG_TC0_SR0 (0x40010020) /**< \brief (TC0) Status Register Channel 0 */ macro
80 #define REG_TC0_SR0 (*(RoReg *)0x40010020UL) /**< \brief (TC0) Status Register Chan… macro
/hal_atmel-3.6.0/asf/sam/include/sam4s/instance/
Dtc0.h42 …#define REG_TC0_SR0 (0x40010020U) /**< \brief (TC0) Status Register (channel = … macro
84 …#define REG_TC0_SR0 (*(__I uint32_t*)0x40010020U) /**< \brief (TC0) Status Register (channel = … macro
/hal_atmel-3.6.0/asf/sam/include/sam3x/instance/
Dtc0.h42 …#define REG_TC0_SR0 (0x40080020U) /**< \brief (TC0) Status Register (channel = … macro
84 …#define REG_TC0_SR0 (*(__I uint32_t*)0x40080020U) /**< \brief (TC0) Status Register (channel = … macro
/hal_atmel-3.6.0/asf/sam/include/sam4e/instance/
Dtc0.h43 #define REG_TC0_SR0 (0x40090020U) /**< \brief (TC0) Status Register (channel = 0) */ macro
109 #define REG_TC0_SR0 (*(RoReg*)0x40090020U) /**< \brief (TC0) Status Register (channel = 0) */ macro
/hal_atmel-3.6.0/asf/sam/include/same70/instance/
Dtc0.h45 #define REG_TC0_SR0 (0x4000C020) /**< (TC0) Status Register (channel = 0) 0 */ macro
95 #define REG_TC0_SR0 (*(__I uint32_t*)0x4000C020U) /**< (TC0) Status Register (channel … macro
/hal_atmel-3.6.0/asf/sam/include/samv71/instance/
Dtc0.h45 #define REG_TC0_SR0 (0x4000C020) /**< (TC0) Status Register (channel = 0) 0 */ macro
96 #define REG_TC0_SR0 (*(__I uint32_t*)0x4000C020U) /**< (TC0) Status Register (channel … macro
/hal_atmel-3.6.0/asf/sam/include/samv71b/instance/
Dtc0.h45 #define REG_TC0_SR0 (0x4000C020) /**< (TC0) Status Register (channel = 0) 0 */ macro
95 #define REG_TC0_SR0 (*(__I uint32_t*)0x4000C020U) /**< (TC0) Status Register (channel … macro
/hal_atmel-3.6.0/asf/sam/include/same70b/instance/
Dtc0.h45 #define REG_TC0_SR0 (0x4000C020) /**< (TC0) Status Register (channel = 0) 0 */ macro
95 #define REG_TC0_SR0 (*(__I uint32_t*)0x4000C020U) /**< (TC0) Status Register (channel … macro