1 /** 2 * \file 3 * 4 * \brief Instance description for TC0 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_TC0_INSTANCE_H_ 32 #define _SAMV71_TC0_INSTANCE_H_ 33 34 /* ========== Register definition for TC0 peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_TC0_CCR0 (0x4000C000) /**< (TC0) Channel Control Register (channel = 0) 0 */ 38 #define REG_TC0_CMR0 (0x4000C004) /**< (TC0) Channel Mode Register (channel = 0) 0 */ 39 #define REG_TC0_SMMR0 (0x4000C008) /**< (TC0) Stepper Motor Mode Register (channel = 0) 0 */ 40 #define REG_TC0_RAB0 (0x4000C00C) /**< (TC0) Register AB (channel = 0) 0 */ 41 #define REG_TC0_CV0 (0x4000C010) /**< (TC0) Counter Value (channel = 0) 0 */ 42 #define REG_TC0_RA0 (0x4000C014) /**< (TC0) Register A (channel = 0) 0 */ 43 #define REG_TC0_RB0 (0x4000C018) /**< (TC0) Register B (channel = 0) 0 */ 44 #define REG_TC0_RC0 (0x4000C01C) /**< (TC0) Register C (channel = 0) 0 */ 45 #define REG_TC0_SR0 (0x4000C020) /**< (TC0) Status Register (channel = 0) 0 */ 46 #define REG_TC0_IER0 (0x4000C024) /**< (TC0) Interrupt Enable Register (channel = 0) 0 */ 47 #define REG_TC0_IDR0 (0x4000C028) /**< (TC0) Interrupt Disable Register (channel = 0) 0 */ 48 #define REG_TC0_IMR0 (0x4000C02C) /**< (TC0) Interrupt Mask Register (channel = 0) 0 */ 49 #define REG_TC0_EMR0 (0x4000C030) /**< (TC0) Extended Mode Register (channel = 0) 0 */ 50 #define REG_TC0_CCR1 (0x4000C040) /**< (TC0) Channel Control Register (channel = 0) 1 */ 51 #define REG_TC0_CMR1 (0x4000C044) /**< (TC0) Channel Mode Register (channel = 0) 1 */ 52 #define REG_TC0_SMMR1 (0x4000C048) /**< (TC0) Stepper Motor Mode Register (channel = 0) 1 */ 53 #define REG_TC0_RAB1 (0x4000C04C) /**< (TC0) Register AB (channel = 0) 1 */ 54 #define REG_TC0_CV1 (0x4000C050) /**< (TC0) Counter Value (channel = 0) 1 */ 55 #define REG_TC0_RA1 (0x4000C054) /**< (TC0) Register A (channel = 0) 1 */ 56 #define REG_TC0_RB1 (0x4000C058) /**< (TC0) Register B (channel = 0) 1 */ 57 #define REG_TC0_RC1 (0x4000C05C) /**< (TC0) Register C (channel = 0) 1 */ 58 #define REG_TC0_SR1 (0x4000C060) /**< (TC0) Status Register (channel = 0) 1 */ 59 #define REG_TC0_IER1 (0x4000C064) /**< (TC0) Interrupt Enable Register (channel = 0) 1 */ 60 #define REG_TC0_IDR1 (0x4000C068) /**< (TC0) Interrupt Disable Register (channel = 0) 1 */ 61 #define REG_TC0_IMR1 (0x4000C06C) /**< (TC0) Interrupt Mask Register (channel = 0) 1 */ 62 #define REG_TC0_EMR1 (0x4000C070) /**< (TC0) Extended Mode Register (channel = 0) 1 */ 63 #define REG_TC0_CCR2 (0x4000C080) /**< (TC0) Channel Control Register (channel = 0) 2 */ 64 #define REG_TC0_CMR2 (0x4000C084) /**< (TC0) Channel Mode Register (channel = 0) 2 */ 65 #define REG_TC0_SMMR2 (0x4000C088) /**< (TC0) Stepper Motor Mode Register (channel = 0) 2 */ 66 #define REG_TC0_RAB2 (0x4000C08C) /**< (TC0) Register AB (channel = 0) 2 */ 67 #define REG_TC0_CV2 (0x4000C090) /**< (TC0) Counter Value (channel = 0) 2 */ 68 #define REG_TC0_RA2 (0x4000C094) /**< (TC0) Register A (channel = 0) 2 */ 69 #define REG_TC0_RB2 (0x4000C098) /**< (TC0) Register B (channel = 0) 2 */ 70 #define REG_TC0_RC2 (0x4000C09C) /**< (TC0) Register C (channel = 0) 2 */ 71 #define REG_TC0_SR2 (0x4000C0A0) /**< (TC0) Status Register (channel = 0) 2 */ 72 #define REG_TC0_IER2 (0x4000C0A4) /**< (TC0) Interrupt Enable Register (channel = 0) 2 */ 73 #define REG_TC0_IDR2 (0x4000C0A8) /**< (TC0) Interrupt Disable Register (channel = 0) 2 */ 74 #define REG_TC0_IMR2 (0x4000C0AC) /**< (TC0) Interrupt Mask Register (channel = 0) 2 */ 75 #define REG_TC0_EMR2 (0x4000C0B0) /**< (TC0) Extended Mode Register (channel = 0) 2 */ 76 #define REG_TC0_BCR (0x4000C0C0) /**< (TC0) Block Control Register */ 77 #define REG_TC0_BMR (0x4000C0C4) /**< (TC0) Block Mode Register */ 78 #define REG_TC0_QIER (0x4000C0C8) /**< (TC0) QDEC Interrupt Enable Register */ 79 #define REG_TC0_QIDR (0x4000C0CC) /**< (TC0) QDEC Interrupt Disable Register */ 80 #define REG_TC0_QIMR (0x4000C0D0) /**< (TC0) QDEC Interrupt Mask Register */ 81 #define REG_TC0_QISR (0x4000C0D4) /**< (TC0) QDEC Interrupt Status Register */ 82 #define REG_TC0_FMR (0x4000C0D8) /**< (TC0) Fault Mode Register */ 83 #define REG_TC0_WPMR (0x4000C0E4) /**< (TC0) Write Protection Mode Register */ 84 85 #else 86 87 #define REG_TC0_CCR0 (*(__O uint32_t*)0x4000C000U) /**< (TC0) Channel Control Register (channel = 0) 0 */ 88 #define REG_TC0_CMR0 (*(__IO uint32_t*)0x4000C004U) /**< (TC0) Channel Mode Register (channel = 0) 0 */ 89 #define REG_TC0_SMMR0 (*(__IO uint32_t*)0x4000C008U) /**< (TC0) Stepper Motor Mode Register (channel = 0) 0 */ 90 #define REG_TC0_RAB0 (*(__I uint32_t*)0x4000C00CU) /**< (TC0) Register AB (channel = 0) 0 */ 91 #define REG_TC0_CV0 (*(__I uint32_t*)0x4000C010U) /**< (TC0) Counter Value (channel = 0) 0 */ 92 #define REG_TC0_RA0 (*(__IO uint32_t*)0x4000C014U) /**< (TC0) Register A (channel = 0) 0 */ 93 #define REG_TC0_RB0 (*(__IO uint32_t*)0x4000C018U) /**< (TC0) Register B (channel = 0) 0 */ 94 #define REG_TC0_RC0 (*(__IO uint32_t*)0x4000C01CU) /**< (TC0) Register C (channel = 0) 0 */ 95 #define REG_TC0_SR0 (*(__I uint32_t*)0x4000C020U) /**< (TC0) Status Register (channel = 0) 0 */ 96 #define REG_TC0_IER0 (*(__O uint32_t*)0x4000C024U) /**< (TC0) Interrupt Enable Register (channel = 0) 0 */ 97 #define REG_TC0_IDR0 (*(__O uint32_t*)0x4000C028U) /**< (TC0) Interrupt Disable Register (channel = 0) 0 */ 98 #define REG_TC0_IMR0 (*(__I uint32_t*)0x4000C02CU) /**< (TC0) Interrupt Mask Register (channel = 0) 0 */ 99 #define REG_TC0_EMR0 (*(__IO uint32_t*)0x4000C030U) /**< (TC0) Extended Mode Register (channel = 0) 0 */ 100 #define REG_TC0_CCR1 (*(__O uint32_t*)0x4000C040U) /**< (TC0) Channel Control Register (channel = 0) 1 */ 101 #define REG_TC0_CMR1 (*(__IO uint32_t*)0x4000C044U) /**< (TC0) Channel Mode Register (channel = 0) 1 */ 102 #define REG_TC0_SMMR1 (*(__IO uint32_t*)0x4000C048U) /**< (TC0) Stepper Motor Mode Register (channel = 0) 1 */ 103 #define REG_TC0_RAB1 (*(__I uint32_t*)0x4000C04CU) /**< (TC0) Register AB (channel = 0) 1 */ 104 #define REG_TC0_CV1 (*(__I uint32_t*)0x4000C050U) /**< (TC0) Counter Value (channel = 0) 1 */ 105 #define REG_TC0_RA1 (*(__IO uint32_t*)0x4000C054U) /**< (TC0) Register A (channel = 0) 1 */ 106 #define REG_TC0_RB1 (*(__IO uint32_t*)0x4000C058U) /**< (TC0) Register B (channel = 0) 1 */ 107 #define REG_TC0_RC1 (*(__IO uint32_t*)0x4000C05CU) /**< (TC0) Register C (channel = 0) 1 */ 108 #define REG_TC0_SR1 (*(__I uint32_t*)0x4000C060U) /**< (TC0) Status Register (channel = 0) 1 */ 109 #define REG_TC0_IER1 (*(__O uint32_t*)0x4000C064U) /**< (TC0) Interrupt Enable Register (channel = 0) 1 */ 110 #define REG_TC0_IDR1 (*(__O uint32_t*)0x4000C068U) /**< (TC0) Interrupt Disable Register (channel = 0) 1 */ 111 #define REG_TC0_IMR1 (*(__I uint32_t*)0x4000C06CU) /**< (TC0) Interrupt Mask Register (channel = 0) 1 */ 112 #define REG_TC0_EMR1 (*(__IO uint32_t*)0x4000C070U) /**< (TC0) Extended Mode Register (channel = 0) 1 */ 113 #define REG_TC0_CCR2 (*(__O uint32_t*)0x4000C080U) /**< (TC0) Channel Control Register (channel = 0) 2 */ 114 #define REG_TC0_CMR2 (*(__IO uint32_t*)0x4000C084U) /**< (TC0) Channel Mode Register (channel = 0) 2 */ 115 #define REG_TC0_SMMR2 (*(__IO uint32_t*)0x4000C088U) /**< (TC0) Stepper Motor Mode Register (channel = 0) 2 */ 116 #define REG_TC0_RAB2 (*(__I uint32_t*)0x4000C08CU) /**< (TC0) Register AB (channel = 0) 2 */ 117 #define REG_TC0_CV2 (*(__I uint32_t*)0x4000C090U) /**< (TC0) Counter Value (channel = 0) 2 */ 118 #define REG_TC0_RA2 (*(__IO uint32_t*)0x4000C094U) /**< (TC0) Register A (channel = 0) 2 */ 119 #define REG_TC0_RB2 (*(__IO uint32_t*)0x4000C098U) /**< (TC0) Register B (channel = 0) 2 */ 120 #define REG_TC0_RC2 (*(__IO uint32_t*)0x4000C09CU) /**< (TC0) Register C (channel = 0) 2 */ 121 #define REG_TC0_SR2 (*(__I uint32_t*)0x4000C0A0U) /**< (TC0) Status Register (channel = 0) 2 */ 122 #define REG_TC0_IER2 (*(__O uint32_t*)0x4000C0A4U) /**< (TC0) Interrupt Enable Register (channel = 0) 2 */ 123 #define REG_TC0_IDR2 (*(__O uint32_t*)0x4000C0A8U) /**< (TC0) Interrupt Disable Register (channel = 0) 2 */ 124 #define REG_TC0_IMR2 (*(__I uint32_t*)0x4000C0ACU) /**< (TC0) Interrupt Mask Register (channel = 0) 2 */ 125 #define REG_TC0_EMR2 (*(__IO uint32_t*)0x4000C0B0U) /**< (TC0) Extended Mode Register (channel = 0) 2 */ 126 #define REG_TC0_BCR (*(__O uint32_t*)0x4000C0C0U) /**< (TC0) Block Control Register */ 127 #define REG_TC0_BMR (*(__IO uint32_t*)0x4000C0C4U) /**< (TC0) Block Mode Register */ 128 #define REG_TC0_QIER (*(__O uint32_t*)0x4000C0C8U) /**< (TC0) QDEC Interrupt Enable Register */ 129 #define REG_TC0_QIDR (*(__O uint32_t*)0x4000C0CCU) /**< (TC0) QDEC Interrupt Disable Register */ 130 #define REG_TC0_QIMR (*(__I uint32_t*)0x4000C0D0U) /**< (TC0) QDEC Interrupt Mask Register */ 131 #define REG_TC0_QISR (*(__I uint32_t*)0x4000C0D4U) /**< (TC0) QDEC Interrupt Status Register */ 132 #define REG_TC0_FMR (*(__IO uint32_t*)0x4000C0D8U) /**< (TC0) Fault Mode Register */ 133 #define REG_TC0_WPMR (*(__IO uint32_t*)0x4000C0E4U) /**< (TC0) Write Protection Mode Register */ 134 135 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 136 137 /* ========== Instance Parameter definitions for TC0 peripheral ========== */ 138 #define TC0_DMAC_ID_RX 40 139 #define TC0_INSTANCE_ID_CHANNEL0 23 140 #define TC0_INSTANCE_ID_CHANNEL1 24 141 #define TC0_INSTANCE_ID_CHANNEL2 25 142 #define TC0_CLOCK_ID_CHANNEL0 23 143 #define TC0_CLOCK_ID_CHANNEL1 24 144 #define TC0_CLOCK_ID_CHANNEL2 25 145 #define TC0_TCCLKS_ 0 /* MCK */ 146 #define TC0_TCCLKS_TIMER_CLOCK1 1 /* PCK */ 147 #define TC0_TCCLKS_TIMER_CLOCK2 2 /* MCK/8 */ 148 #define TC0_TCCLKS_TIMER_CLOCK3 3 /* MCK/32 */ 149 #define TC0_TCCLKS_TIMER_CLOCK4 4 /* MCK/128 */ 150 #define TC0_TCCLKS_TIMER_CLOCK5 5 /* SLCK */ 151 #define TC0_TCCLKS_XC0 6 /* XC0 */ 152 #define TC0_TCCLKS_XC1 7 /* XC1 */ 153 #define TC0_TCCLKS_XC2 8 /* XC2 */ 154 #define TC0_NUM_INTERRUPT_LINES 3 155 #define TC0_TIMER_WIDTH 16 156 157 #endif /* _SAMV71_TC0_INSTANCE_ */ 158
