1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM3XA_TC0_INSTANCE_ 31 #define _SAM3XA_TC0_INSTANCE_ 32 33 /* ========== Register definition for TC0 peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_TC0_CCR0 (0x40080000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ 36 #define REG_TC0_CMR0 (0x40080004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ 37 #define REG_TC0_SMMR0 (0x40080008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */ 38 #define REG_TC0_CV0 (0x40080010U) /**< \brief (TC0) Counter Value (channel = 0) */ 39 #define REG_TC0_RA0 (0x40080014U) /**< \brief (TC0) Register A (channel = 0) */ 40 #define REG_TC0_RB0 (0x40080018U) /**< \brief (TC0) Register B (channel = 0) */ 41 #define REG_TC0_RC0 (0x4008001CU) /**< \brief (TC0) Register C (channel = 0) */ 42 #define REG_TC0_SR0 (0x40080020U) /**< \brief (TC0) Status Register (channel = 0) */ 43 #define REG_TC0_IER0 (0x40080024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ 44 #define REG_TC0_IDR0 (0x40080028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ 45 #define REG_TC0_IMR0 (0x4008002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ 46 #define REG_TC0_CCR1 (0x40080040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ 47 #define REG_TC0_CMR1 (0x40080044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ 48 #define REG_TC0_SMMR1 (0x40080048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */ 49 #define REG_TC0_CV1 (0x40080050U) /**< \brief (TC0) Counter Value (channel = 1) */ 50 #define REG_TC0_RA1 (0x40080054U) /**< \brief (TC0) Register A (channel = 1) */ 51 #define REG_TC0_RB1 (0x40080058U) /**< \brief (TC0) Register B (channel = 1) */ 52 #define REG_TC0_RC1 (0x4008005CU) /**< \brief (TC0) Register C (channel = 1) */ 53 #define REG_TC0_SR1 (0x40080060U) /**< \brief (TC0) Status Register (channel = 1) */ 54 #define REG_TC0_IER1 (0x40080064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ 55 #define REG_TC0_IDR1 (0x40080068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ 56 #define REG_TC0_IMR1 (0x4008006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ 57 #define REG_TC0_CCR2 (0x40080080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ 58 #define REG_TC0_CMR2 (0x40080084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ 59 #define REG_TC0_SMMR2 (0x40080088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */ 60 #define REG_TC0_CV2 (0x40080090U) /**< \brief (TC0) Counter Value (channel = 2) */ 61 #define REG_TC0_RA2 (0x40080094U) /**< \brief (TC0) Register A (channel = 2) */ 62 #define REG_TC0_RB2 (0x40080098U) /**< \brief (TC0) Register B (channel = 2) */ 63 #define REG_TC0_RC2 (0x4008009CU) /**< \brief (TC0) Register C (channel = 2) */ 64 #define REG_TC0_SR2 (0x400800A0U) /**< \brief (TC0) Status Register (channel = 2) */ 65 #define REG_TC0_IER2 (0x400800A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ 66 #define REG_TC0_IDR2 (0x400800A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ 67 #define REG_TC0_IMR2 (0x400800ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ 68 #define REG_TC0_BCR (0x400800C0U) /**< \brief (TC0) Block Control Register */ 69 #define REG_TC0_BMR (0x400800C4U) /**< \brief (TC0) Block Mode Register */ 70 #define REG_TC0_QIER (0x400800C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ 71 #define REG_TC0_QIDR (0x400800CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ 72 #define REG_TC0_QIMR (0x400800D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ 73 #define REG_TC0_QISR (0x400800D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ 74 #define REG_TC0_FMR (0x400800D8U) /**< \brief (TC0) Fault Mode Register */ 75 #define REG_TC0_WPMR (0x400800E4U) /**< \brief (TC0) Write Protect Mode Register */ 76 #else 77 #define REG_TC0_CCR0 (*(__O uint32_t*)0x40080000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ 78 #define REG_TC0_CMR0 (*(__IO uint32_t*)0x40080004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ 79 #define REG_TC0_SMMR0 (*(__IO uint32_t*)0x40080008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */ 80 #define REG_TC0_CV0 (*(__I uint32_t*)0x40080010U) /**< \brief (TC0) Counter Value (channel = 0) */ 81 #define REG_TC0_RA0 (*(__IO uint32_t*)0x40080014U) /**< \brief (TC0) Register A (channel = 0) */ 82 #define REG_TC0_RB0 (*(__IO uint32_t*)0x40080018U) /**< \brief (TC0) Register B (channel = 0) */ 83 #define REG_TC0_RC0 (*(__IO uint32_t*)0x4008001CU) /**< \brief (TC0) Register C (channel = 0) */ 84 #define REG_TC0_SR0 (*(__I uint32_t*)0x40080020U) /**< \brief (TC0) Status Register (channel = 0) */ 85 #define REG_TC0_IER0 (*(__O uint32_t*)0x40080024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ 86 #define REG_TC0_IDR0 (*(__O uint32_t*)0x40080028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ 87 #define REG_TC0_IMR0 (*(__I uint32_t*)0x4008002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ 88 #define REG_TC0_CCR1 (*(__O uint32_t*)0x40080040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ 89 #define REG_TC0_CMR1 (*(__IO uint32_t*)0x40080044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ 90 #define REG_TC0_SMMR1 (*(__IO uint32_t*)0x40080048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */ 91 #define REG_TC0_CV1 (*(__I uint32_t*)0x40080050U) /**< \brief (TC0) Counter Value (channel = 1) */ 92 #define REG_TC0_RA1 (*(__IO uint32_t*)0x40080054U) /**< \brief (TC0) Register A (channel = 1) */ 93 #define REG_TC0_RB1 (*(__IO uint32_t*)0x40080058U) /**< \brief (TC0) Register B (channel = 1) */ 94 #define REG_TC0_RC1 (*(__IO uint32_t*)0x4008005CU) /**< \brief (TC0) Register C (channel = 1) */ 95 #define REG_TC0_SR1 (*(__I uint32_t*)0x40080060U) /**< \brief (TC0) Status Register (channel = 1) */ 96 #define REG_TC0_IER1 (*(__O uint32_t*)0x40080064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ 97 #define REG_TC0_IDR1 (*(__O uint32_t*)0x40080068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ 98 #define REG_TC0_IMR1 (*(__I uint32_t*)0x4008006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ 99 #define REG_TC0_CCR2 (*(__O uint32_t*)0x40080080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ 100 #define REG_TC0_CMR2 (*(__IO uint32_t*)0x40080084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ 101 #define REG_TC0_SMMR2 (*(__IO uint32_t*)0x40080088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */ 102 #define REG_TC0_CV2 (*(__I uint32_t*)0x40080090U) /**< \brief (TC0) Counter Value (channel = 2) */ 103 #define REG_TC0_RA2 (*(__IO uint32_t*)0x40080094U) /**< \brief (TC0) Register A (channel = 2) */ 104 #define REG_TC0_RB2 (*(__IO uint32_t*)0x40080098U) /**< \brief (TC0) Register B (channel = 2) */ 105 #define REG_TC0_RC2 (*(__IO uint32_t*)0x4008009CU) /**< \brief (TC0) Register C (channel = 2) */ 106 #define REG_TC0_SR2 (*(__I uint32_t*)0x400800A0U) /**< \brief (TC0) Status Register (channel = 2) */ 107 #define REG_TC0_IER2 (*(__O uint32_t*)0x400800A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ 108 #define REG_TC0_IDR2 (*(__O uint32_t*)0x400800A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ 109 #define REG_TC0_IMR2 (*(__I uint32_t*)0x400800ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ 110 #define REG_TC0_BCR (*(__O uint32_t*)0x400800C0U) /**< \brief (TC0) Block Control Register */ 111 #define REG_TC0_BMR (*(__IO uint32_t*)0x400800C4U) /**< \brief (TC0) Block Mode Register */ 112 #define REG_TC0_QIER (*(__O uint32_t*)0x400800C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ 113 #define REG_TC0_QIDR (*(__O uint32_t*)0x400800CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ 114 #define REG_TC0_QIMR (*(__I uint32_t*)0x400800D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ 115 #define REG_TC0_QISR (*(__I uint32_t*)0x400800D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ 116 #define REG_TC0_FMR (*(__IO uint32_t*)0x400800D8U) /**< \brief (TC0) Fault Mode Register */ 117 #define REG_TC0_WPMR (*(__IO uint32_t*)0x400800E4U) /**< \brief (TC0) Write Protect Mode Register */ 118 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 119 120 #endif /* _SAM3XA_TC0_INSTANCE_ */ 121
