/hal_atmel-3.5.0-3.4.0/asf/sam0/include/samd20/pio/ |
D | samd20e18.h | 91 #define MUX_PA27H_GCLK_IO0 _L_(7) macro 92 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
D | samd20e15.h | 91 #define MUX_PA27H_GCLK_IO0 _L_(7) macro 92 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
D | samd20e16.h | 91 #define MUX_PA27H_GCLK_IO0 _L_(7) macro 92 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
D | samd20e17.h | 91 #define MUX_PA27H_GCLK_IO0 _L_(7) macro 92 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
D | samd20e14.h | 91 #define MUX_PA27H_GCLK_IO0 _L_(7) macro 92 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
D | samd20g18u.h | 109 #define MUX_PA27H_GCLK_IO0 _L_(7) macro 110 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
D | samd20g17u.h | 109 #define MUX_PA27H_GCLK_IO0 _L_(7) macro 110 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
D | samd20g14.h | 119 #define MUX_PA27H_GCLK_IO0 _L_(7) macro 120 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
D | samd20g15.h | 119 #define MUX_PA27H_GCLK_IO0 _L_(7) macro 120 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
D | samd20g16.h | 119 #define MUX_PA27H_GCLK_IO0 _L_(7) macro 120 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
D | samd20g17.h | 119 #define MUX_PA27H_GCLK_IO0 _L_(7) macro 120 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
/hal_atmel-3.5.0-3.4.0/asf/sam0/include/samd21/pio/ |
D | samd21e18a.h | 90 #define MUX_PA27H_GCLK_IO0 _L_(7) macro 91 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
D | samd21e15a.h | 90 #define MUX_PA27H_GCLK_IO0 _L_(7) macro 91 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
D | samd21e16a.h | 90 #define MUX_PA27H_GCLK_IO0 _L_(7) macro 91 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
D | samd21e17a.h | 90 #define MUX_PA27H_GCLK_IO0 _L_(7) macro 91 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
/hal_atmel-3.5.0-3.4.0/asf/sam0/include/samr21/pio/ |
D | samr21e16a.h | 104 #define MUX_PA27H_GCLK_IO0 _L_(7) macro 105 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
D | samr21e17a.h | 104 #define MUX_PA27H_GCLK_IO0 _L_(7) macro 105 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
D | samr21e18a.h | 104 #define MUX_PA27H_GCLK_IO0 _L_(7) macro 105 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
/hal_atmel-3.5.0-3.4.0/asf/sam0/include/samc20/pio/ |
D | samc20e15a.h | 148 #define MUX_PA27H_GCLK_IO0 _L_(7) macro 149 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
D | samc20e16a.h | 148 #define MUX_PA27H_GCLK_IO0 _L_(7) macro 149 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
D | samc20e17a.h | 148 #define MUX_PA27H_GCLK_IO0 _L_(7) macro 149 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
D | samc20e18a.h | 148 #define MUX_PA27H_GCLK_IO0 _L_(7) macro 149 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
/hal_atmel-3.5.0-3.4.0/asf/sam0/include/saml21/pio/ |
D | saml21e15b.h | 122 #define MUX_PA27H_GCLK_IO0 _L_(7) macro 123 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
D | saml21e16b.h | 122 #define MUX_PA27H_GCLK_IO0 _L_(7) macro 123 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
D | saml21e17b.h | 122 #define MUX_PA27H_GCLK_IO0 _L_(7) macro 123 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|