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Searched refs:MUX_PA27H_GCLK_IO0 (Results 1 – 25 of 88) sorted by relevance

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/hal_atmel-3.5.0-3.4.0/asf/sam0/include/samd20/pio/
Dsamd20e18.h91 #define MUX_PA27H_GCLK_IO0 _L_(7) macro
92 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
Dsamd20e15.h91 #define MUX_PA27H_GCLK_IO0 _L_(7) macro
92 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
Dsamd20e16.h91 #define MUX_PA27H_GCLK_IO0 _L_(7) macro
92 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
Dsamd20e17.h91 #define MUX_PA27H_GCLK_IO0 _L_(7) macro
92 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
Dsamd20e14.h91 #define MUX_PA27H_GCLK_IO0 _L_(7) macro
92 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
Dsamd20g18u.h109 #define MUX_PA27H_GCLK_IO0 _L_(7) macro
110 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
Dsamd20g17u.h109 #define MUX_PA27H_GCLK_IO0 _L_(7) macro
110 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
Dsamd20g14.h119 #define MUX_PA27H_GCLK_IO0 _L_(7) macro
120 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
Dsamd20g15.h119 #define MUX_PA27H_GCLK_IO0 _L_(7) macro
120 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
Dsamd20g16.h119 #define MUX_PA27H_GCLK_IO0 _L_(7) macro
120 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
Dsamd20g17.h119 #define MUX_PA27H_GCLK_IO0 _L_(7) macro
120 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
/hal_atmel-3.5.0-3.4.0/asf/sam0/include/samd21/pio/
Dsamd21e18a.h90 #define MUX_PA27H_GCLK_IO0 _L_(7) macro
91 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
Dsamd21e15a.h90 #define MUX_PA27H_GCLK_IO0 _L_(7) macro
91 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
Dsamd21e16a.h90 #define MUX_PA27H_GCLK_IO0 _L_(7) macro
91 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
Dsamd21e17a.h90 #define MUX_PA27H_GCLK_IO0 _L_(7) macro
91 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
/hal_atmel-3.5.0-3.4.0/asf/sam0/include/samr21/pio/
Dsamr21e16a.h104 #define MUX_PA27H_GCLK_IO0 _L_(7) macro
105 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
Dsamr21e17a.h104 #define MUX_PA27H_GCLK_IO0 _L_(7) macro
105 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
Dsamr21e18a.h104 #define MUX_PA27H_GCLK_IO0 _L_(7) macro
105 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
/hal_atmel-3.5.0-3.4.0/asf/sam0/include/samc20/pio/
Dsamc20e15a.h148 #define MUX_PA27H_GCLK_IO0 _L_(7) macro
149 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
Dsamc20e16a.h148 #define MUX_PA27H_GCLK_IO0 _L_(7) macro
149 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
Dsamc20e17a.h148 #define MUX_PA27H_GCLK_IO0 _L_(7) macro
149 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
Dsamc20e18a.h148 #define MUX_PA27H_GCLK_IO0 _L_(7) macro
149 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
/hal_atmel-3.5.0-3.4.0/asf/sam0/include/saml21/pio/
Dsaml21e15b.h122 #define MUX_PA27H_GCLK_IO0 _L_(7) macro
123 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
Dsaml21e16b.h122 #define MUX_PA27H_GCLK_IO0 _L_(7) macro
123 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
Dsaml21e17b.h122 #define MUX_PA27H_GCLK_IO0 _L_(7) macro
123 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)

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