1 /**
2  * \file
3  *
4  * \brief Peripheral I/O description for SAMD20E16
5  *
6  * Copyright (c) 2017 Microchip Technology Inc.
7  *
8  * \asf_license_start
9  *
10  * \page License
11  *
12  * SPDX-License-Identifier: Apache-2.0
13  *
14  * Licensed under the Apache License, Version 2.0 (the "License"); you may
15  * not use this file except in compliance with the License.
16  * You may obtain a copy of the Licence at
17  *
18  * http://www.apache.org/licenses/LICENSE-2.0
19  *
20  * Unless required by applicable law or agreed to in writing, software
21  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
22  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23  * See the License for the specific language governing permissions and
24  * limitations under the License.
25  *
26  * \asf_license_stop
27  *
28  */
29 
30 #ifndef _SAMD20E16_PIO_
31 #define _SAMD20E16_PIO_
32 
33 #define PIN_PA00                            0  /**< \brief Pin Number for PA00 */
34 #define PORT_PA00              (_UL_(1) <<  0) /**< \brief PORT Mask  for PA00 */
35 #define PIN_PA01                            1  /**< \brief Pin Number for PA01 */
36 #define PORT_PA01              (_UL_(1) <<  1) /**< \brief PORT Mask  for PA01 */
37 #define PIN_PA02                            2  /**< \brief Pin Number for PA02 */
38 #define PORT_PA02              (_UL_(1) <<  2) /**< \brief PORT Mask  for PA02 */
39 #define PIN_PA03                            3  /**< \brief Pin Number for PA03 */
40 #define PORT_PA03              (_UL_(1) <<  3) /**< \brief PORT Mask  for PA03 */
41 #define PIN_PA04                            4  /**< \brief Pin Number for PA04 */
42 #define PORT_PA04              (_UL_(1) <<  4) /**< \brief PORT Mask  for PA04 */
43 #define PIN_PA05                            5  /**< \brief Pin Number for PA05 */
44 #define PORT_PA05              (_UL_(1) <<  5) /**< \brief PORT Mask  for PA05 */
45 #define PIN_PA06                            6  /**< \brief Pin Number for PA06 */
46 #define PORT_PA06              (_UL_(1) <<  6) /**< \brief PORT Mask  for PA06 */
47 #define PIN_PA07                            7  /**< \brief Pin Number for PA07 */
48 #define PORT_PA07              (_UL_(1) <<  7) /**< \brief PORT Mask  for PA07 */
49 #define PIN_PA08                            8  /**< \brief Pin Number for PA08 */
50 #define PORT_PA08              (_UL_(1) <<  8) /**< \brief PORT Mask  for PA08 */
51 #define PIN_PA09                            9  /**< \brief Pin Number for PA09 */
52 #define PORT_PA09              (_UL_(1) <<  9) /**< \brief PORT Mask  for PA09 */
53 #define PIN_PA10                           10  /**< \brief Pin Number for PA10 */
54 #define PORT_PA10              (_UL_(1) << 10) /**< \brief PORT Mask  for PA10 */
55 #define PIN_PA11                           11  /**< \brief Pin Number for PA11 */
56 #define PORT_PA11              (_UL_(1) << 11) /**< \brief PORT Mask  for PA11 */
57 #define PIN_PA14                           14  /**< \brief Pin Number for PA14 */
58 #define PORT_PA14              (_UL_(1) << 14) /**< \brief PORT Mask  for PA14 */
59 #define PIN_PA15                           15  /**< \brief Pin Number for PA15 */
60 #define PORT_PA15              (_UL_(1) << 15) /**< \brief PORT Mask  for PA15 */
61 #define PIN_PA16                           16  /**< \brief Pin Number for PA16 */
62 #define PORT_PA16              (_UL_(1) << 16) /**< \brief PORT Mask  for PA16 */
63 #define PIN_PA17                           17  /**< \brief Pin Number for PA17 */
64 #define PORT_PA17              (_UL_(1) << 17) /**< \brief PORT Mask  for PA17 */
65 #define PIN_PA18                           18  /**< \brief Pin Number for PA18 */
66 #define PORT_PA18              (_UL_(1) << 18) /**< \brief PORT Mask  for PA18 */
67 #define PIN_PA19                           19  /**< \brief Pin Number for PA19 */
68 #define PORT_PA19              (_UL_(1) << 19) /**< \brief PORT Mask  for PA19 */
69 #define PIN_PA22                           22  /**< \brief Pin Number for PA22 */
70 #define PORT_PA22              (_UL_(1) << 22) /**< \brief PORT Mask  for PA22 */
71 #define PIN_PA23                           23  /**< \brief Pin Number for PA23 */
72 #define PORT_PA23              (_UL_(1) << 23) /**< \brief PORT Mask  for PA23 */
73 #define PIN_PA24                           24  /**< \brief Pin Number for PA24 */
74 #define PORT_PA24              (_UL_(1) << 24) /**< \brief PORT Mask  for PA24 */
75 #define PIN_PA25                           25  /**< \brief Pin Number for PA25 */
76 #define PORT_PA25              (_UL_(1) << 25) /**< \brief PORT Mask  for PA25 */
77 #define PIN_PA27                           27  /**< \brief Pin Number for PA27 */
78 #define PORT_PA27              (_UL_(1) << 27) /**< \brief PORT Mask  for PA27 */
79 #define PIN_PA28                           28  /**< \brief Pin Number for PA28 */
80 #define PORT_PA28              (_UL_(1) << 28) /**< \brief PORT Mask  for PA28 */
81 #define PIN_PA30                           30  /**< \brief Pin Number for PA30 */
82 #define PORT_PA30              (_UL_(1) << 30) /**< \brief PORT Mask  for PA30 */
83 #define PIN_PA31                           31  /**< \brief Pin Number for PA31 */
84 #define PORT_PA31              (_UL_(1) << 31) /**< \brief PORT Mask  for PA31 */
85 /* ========== PORT definition for GCLK peripheral ========== */
86 #define PIN_PA14H_GCLK_IO0             _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */
87 #define MUX_PA14H_GCLK_IO0              _L_(7)
88 #define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
89 #define PORT_PA14H_GCLK_IO0    (_UL_(1) << 14)
90 #define PIN_PA27H_GCLK_IO0             _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */
91 #define MUX_PA27H_GCLK_IO0              _L_(7)
92 #define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
93 #define PORT_PA27H_GCLK_IO0    (_UL_(1) << 27)
94 #define PIN_PA28H_GCLK_IO0             _L_(28) /**< \brief GCLK signal: IO0 on PA28 mux H */
95 #define MUX_PA28H_GCLK_IO0              _L_(7)
96 #define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
97 #define PORT_PA28H_GCLK_IO0    (_UL_(1) << 28)
98 #define PIN_PA30H_GCLK_IO0             _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */
99 #define MUX_PA30H_GCLK_IO0              _L_(7)
100 #define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
101 #define PORT_PA30H_GCLK_IO0    (_UL_(1) << 30)
102 #define PIN_PA15H_GCLK_IO1             _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */
103 #define MUX_PA15H_GCLK_IO1              _L_(7)
104 #define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
105 #define PORT_PA15H_GCLK_IO1    (_UL_(1) << 15)
106 #define PIN_PA16H_GCLK_IO2             _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */
107 #define MUX_PA16H_GCLK_IO2              _L_(7)
108 #define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
109 #define PORT_PA16H_GCLK_IO2    (_UL_(1) << 16)
110 #define PIN_PA17H_GCLK_IO3             _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */
111 #define MUX_PA17H_GCLK_IO3              _L_(7)
112 #define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
113 #define PORT_PA17H_GCLK_IO3    (_UL_(1) << 17)
114 #define PIN_PA10H_GCLK_IO4             _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */
115 #define MUX_PA10H_GCLK_IO4              _L_(7)
116 #define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
117 #define PORT_PA10H_GCLK_IO4    (_UL_(1) << 10)
118 #define PIN_PA11H_GCLK_IO5             _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux H */
119 #define MUX_PA11H_GCLK_IO5              _L_(7)
120 #define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
121 #define PORT_PA11H_GCLK_IO5    (_UL_(1) << 11)
122 #define PIN_PA22H_GCLK_IO6             _L_(22) /**< \brief GCLK signal: IO6 on PA22 mux H */
123 #define MUX_PA22H_GCLK_IO6              _L_(7)
124 #define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
125 #define PORT_PA22H_GCLK_IO6    (_UL_(1) << 22)
126 #define PIN_PA23H_GCLK_IO7             _L_(23) /**< \brief GCLK signal: IO7 on PA23 mux H */
127 #define MUX_PA23H_GCLK_IO7              _L_(7)
128 #define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
129 #define PORT_PA23H_GCLK_IO7    (_UL_(1) << 23)
130 /* ========== PORT definition for EIC peripheral ========== */
131 #define PIN_PA16A_EIC_EXTINT0          _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
132 #define MUX_PA16A_EIC_EXTINT0           _L_(0)
133 #define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
134 #define PORT_PA16A_EIC_EXTINT0  (_UL_(1) << 16)
135 #define PIN_PA16A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
136 #define PIN_PA00A_EIC_EXTINT0           _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
137 #define MUX_PA00A_EIC_EXTINT0           _L_(0)
138 #define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
139 #define PORT_PA00A_EIC_EXTINT0  (_UL_(1) <<  0)
140 #define PIN_PA00A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
141 #define PIN_PA17A_EIC_EXTINT1          _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
142 #define MUX_PA17A_EIC_EXTINT1           _L_(0)
143 #define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
144 #define PORT_PA17A_EIC_EXTINT1  (_UL_(1) << 17)
145 #define PIN_PA17A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
146 #define PIN_PA01A_EIC_EXTINT1           _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
147 #define MUX_PA01A_EIC_EXTINT1           _L_(0)
148 #define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
149 #define PORT_PA01A_EIC_EXTINT1  (_UL_(1) <<  1)
150 #define PIN_PA01A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
151 #define PIN_PA02A_EIC_EXTINT2           _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
152 #define MUX_PA02A_EIC_EXTINT2           _L_(0)
153 #define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
154 #define PORT_PA02A_EIC_EXTINT2  (_UL_(1) <<  2)
155 #define PIN_PA02A_EIC_EXTINT_NUM        _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
156 #define PIN_PA18A_EIC_EXTINT2          _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
157 #define MUX_PA18A_EIC_EXTINT2           _L_(0)
158 #define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
159 #define PORT_PA18A_EIC_EXTINT2  (_UL_(1) << 18)
160 #define PIN_PA18A_EIC_EXTINT_NUM        _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
161 #define PIN_PA03A_EIC_EXTINT3           _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
162 #define MUX_PA03A_EIC_EXTINT3           _L_(0)
163 #define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
164 #define PORT_PA03A_EIC_EXTINT3  (_UL_(1) <<  3)
165 #define PIN_PA03A_EIC_EXTINT_NUM        _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
166 #define PIN_PA19A_EIC_EXTINT3          _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
167 #define MUX_PA19A_EIC_EXTINT3           _L_(0)
168 #define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
169 #define PORT_PA19A_EIC_EXTINT3  (_UL_(1) << 19)
170 #define PIN_PA19A_EIC_EXTINT_NUM        _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
171 #define PIN_PA04A_EIC_EXTINT4           _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
172 #define MUX_PA04A_EIC_EXTINT4           _L_(0)
173 #define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
174 #define PORT_PA04A_EIC_EXTINT4  (_UL_(1) <<  4)
175 #define PIN_PA04A_EIC_EXTINT_NUM        _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
176 #define PIN_PA05A_EIC_EXTINT5           _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
177 #define MUX_PA05A_EIC_EXTINT5           _L_(0)
178 #define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
179 #define PORT_PA05A_EIC_EXTINT5  (_UL_(1) <<  5)
180 #define PIN_PA05A_EIC_EXTINT_NUM        _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
181 #define PIN_PA06A_EIC_EXTINT6           _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
182 #define MUX_PA06A_EIC_EXTINT6           _L_(0)
183 #define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
184 #define PORT_PA06A_EIC_EXTINT6  (_UL_(1) <<  6)
185 #define PIN_PA06A_EIC_EXTINT_NUM        _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
186 #define PIN_PA22A_EIC_EXTINT6          _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
187 #define MUX_PA22A_EIC_EXTINT6           _L_(0)
188 #define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
189 #define PORT_PA22A_EIC_EXTINT6  (_UL_(1) << 22)
190 #define PIN_PA22A_EIC_EXTINT_NUM        _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
191 #define PIN_PA07A_EIC_EXTINT7           _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
192 #define MUX_PA07A_EIC_EXTINT7           _L_(0)
193 #define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
194 #define PORT_PA07A_EIC_EXTINT7  (_UL_(1) <<  7)
195 #define PIN_PA07A_EIC_EXTINT_NUM        _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
196 #define PIN_PA23A_EIC_EXTINT7          _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
197 #define MUX_PA23A_EIC_EXTINT7           _L_(0)
198 #define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
199 #define PORT_PA23A_EIC_EXTINT7  (_UL_(1) << 23)
200 #define PIN_PA23A_EIC_EXTINT_NUM        _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
201 #define PIN_PA28A_EIC_EXTINT8          _L_(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */
202 #define MUX_PA28A_EIC_EXTINT8           _L_(0)
203 #define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
204 #define PORT_PA28A_EIC_EXTINT8  (_UL_(1) << 28)
205 #define PIN_PA28A_EIC_EXTINT_NUM        _L_(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
206 #define PIN_PA09A_EIC_EXTINT9           _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
207 #define MUX_PA09A_EIC_EXTINT9           _L_(0)
208 #define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
209 #define PORT_PA09A_EIC_EXTINT9  (_UL_(1) <<  9)
210 #define PIN_PA09A_EIC_EXTINT_NUM        _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
211 #define PIN_PA10A_EIC_EXTINT10         _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
212 #define MUX_PA10A_EIC_EXTINT10          _L_(0)
213 #define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
214 #define PORT_PA10A_EIC_EXTINT10  (_UL_(1) << 10)
215 #define PIN_PA10A_EIC_EXTINT_NUM       _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
216 #define PIN_PA30A_EIC_EXTINT10         _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */
217 #define MUX_PA30A_EIC_EXTINT10          _L_(0)
218 #define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
219 #define PORT_PA30A_EIC_EXTINT10  (_UL_(1) << 30)
220 #define PIN_PA30A_EIC_EXTINT_NUM       _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
221 #define PIN_PA11A_EIC_EXTINT11         _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
222 #define MUX_PA11A_EIC_EXTINT11          _L_(0)
223 #define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
224 #define PORT_PA11A_EIC_EXTINT11  (_UL_(1) << 11)
225 #define PIN_PA11A_EIC_EXTINT_NUM       _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
226 #define PIN_PA31A_EIC_EXTINT11         _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */
227 #define MUX_PA31A_EIC_EXTINT11          _L_(0)
228 #define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
229 #define PORT_PA31A_EIC_EXTINT11  (_UL_(1) << 31)
230 #define PIN_PA31A_EIC_EXTINT_NUM       _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
231 #define PIN_PA24A_EIC_EXTINT12         _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */
232 #define MUX_PA24A_EIC_EXTINT12          _L_(0)
233 #define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
234 #define PORT_PA24A_EIC_EXTINT12  (_UL_(1) << 24)
235 #define PIN_PA24A_EIC_EXTINT_NUM       _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
236 #define PIN_PA25A_EIC_EXTINT13         _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */
237 #define MUX_PA25A_EIC_EXTINT13          _L_(0)
238 #define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
239 #define PORT_PA25A_EIC_EXTINT13  (_UL_(1) << 25)
240 #define PIN_PA25A_EIC_EXTINT_NUM       _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
241 #define PIN_PA14A_EIC_EXTINT14         _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
242 #define MUX_PA14A_EIC_EXTINT14          _L_(0)
243 #define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
244 #define PORT_PA14A_EIC_EXTINT14  (_UL_(1) << 14)
245 #define PIN_PA14A_EIC_EXTINT_NUM       _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
246 #define PIN_PA27A_EIC_EXTINT15         _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */
247 #define MUX_PA27A_EIC_EXTINT15          _L_(0)
248 #define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
249 #define PORT_PA27A_EIC_EXTINT15  (_UL_(1) << 27)
250 #define PIN_PA27A_EIC_EXTINT_NUM       _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
251 #define PIN_PA15A_EIC_EXTINT15         _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
252 #define MUX_PA15A_EIC_EXTINT15          _L_(0)
253 #define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
254 #define PORT_PA15A_EIC_EXTINT15  (_UL_(1) << 15)
255 #define PIN_PA15A_EIC_EXTINT_NUM       _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
256 #define PIN_PA08A_EIC_NMI               _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */
257 #define MUX_PA08A_EIC_NMI               _L_(0)
258 #define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
259 #define PORT_PA08A_EIC_NMI     (_UL_(1) <<  8)
260 /* ========== PORT definition for SERCOM0 peripheral ========== */
261 #define PIN_PA04D_SERCOM0_PAD0          _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
262 #define MUX_PA04D_SERCOM0_PAD0          _L_(3)
263 #define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
264 #define PORT_PA04D_SERCOM0_PAD0  (_UL_(1) <<  4)
265 #define PIN_PA08C_SERCOM0_PAD0          _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
266 #define MUX_PA08C_SERCOM0_PAD0          _L_(2)
267 #define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
268 #define PORT_PA08C_SERCOM0_PAD0  (_UL_(1) <<  8)
269 #define PIN_PA05D_SERCOM0_PAD1          _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
270 #define MUX_PA05D_SERCOM0_PAD1          _L_(3)
271 #define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
272 #define PORT_PA05D_SERCOM0_PAD1  (_UL_(1) <<  5)
273 #define PIN_PA09C_SERCOM0_PAD1          _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
274 #define MUX_PA09C_SERCOM0_PAD1          _L_(2)
275 #define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
276 #define PORT_PA09C_SERCOM0_PAD1  (_UL_(1) <<  9)
277 #define PIN_PA06D_SERCOM0_PAD2          _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
278 #define MUX_PA06D_SERCOM0_PAD2          _L_(3)
279 #define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
280 #define PORT_PA06D_SERCOM0_PAD2  (_UL_(1) <<  6)
281 #define PIN_PA10C_SERCOM0_PAD2         _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
282 #define MUX_PA10C_SERCOM0_PAD2          _L_(2)
283 #define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
284 #define PORT_PA10C_SERCOM0_PAD2  (_UL_(1) << 10)
285 #define PIN_PA07D_SERCOM0_PAD3          _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
286 #define MUX_PA07D_SERCOM0_PAD3          _L_(3)
287 #define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
288 #define PORT_PA07D_SERCOM0_PAD3  (_UL_(1) <<  7)
289 #define PIN_PA11C_SERCOM0_PAD3         _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
290 #define MUX_PA11C_SERCOM0_PAD3          _L_(2)
291 #define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
292 #define PORT_PA11C_SERCOM0_PAD3  (_UL_(1) << 11)
293 /* ========== PORT definition for SERCOM1 peripheral ========== */
294 #define PIN_PA16C_SERCOM1_PAD0         _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
295 #define MUX_PA16C_SERCOM1_PAD0          _L_(2)
296 #define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
297 #define PORT_PA16C_SERCOM1_PAD0  (_UL_(1) << 16)
298 #define PIN_PA00D_SERCOM1_PAD0          _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
299 #define MUX_PA00D_SERCOM1_PAD0          _L_(3)
300 #define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
301 #define PORT_PA00D_SERCOM1_PAD0  (_UL_(1) <<  0)
302 #define PIN_PA17C_SERCOM1_PAD1         _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
303 #define MUX_PA17C_SERCOM1_PAD1          _L_(2)
304 #define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
305 #define PORT_PA17C_SERCOM1_PAD1  (_UL_(1) << 17)
306 #define PIN_PA01D_SERCOM1_PAD1          _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
307 #define MUX_PA01D_SERCOM1_PAD1          _L_(3)
308 #define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
309 #define PORT_PA01D_SERCOM1_PAD1  (_UL_(1) <<  1)
310 #define PIN_PA30D_SERCOM1_PAD2         _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
311 #define MUX_PA30D_SERCOM1_PAD2          _L_(3)
312 #define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
313 #define PORT_PA30D_SERCOM1_PAD2  (_UL_(1) << 30)
314 #define PIN_PA18C_SERCOM1_PAD2         _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
315 #define MUX_PA18C_SERCOM1_PAD2          _L_(2)
316 #define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
317 #define PORT_PA18C_SERCOM1_PAD2  (_UL_(1) << 18)
318 #define PIN_PA31D_SERCOM1_PAD3         _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
319 #define MUX_PA31D_SERCOM1_PAD3          _L_(3)
320 #define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
321 #define PORT_PA31D_SERCOM1_PAD3  (_UL_(1) << 31)
322 #define PIN_PA19C_SERCOM1_PAD3         _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
323 #define MUX_PA19C_SERCOM1_PAD3          _L_(2)
324 #define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
325 #define PORT_PA19C_SERCOM1_PAD3  (_UL_(1) << 19)
326 /* ========== PORT definition for SERCOM2 peripheral ========== */
327 #define PIN_PA08D_SERCOM2_PAD0          _L_(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
328 #define MUX_PA08D_SERCOM2_PAD0          _L_(3)
329 #define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
330 #define PORT_PA08D_SERCOM2_PAD0  (_UL_(1) <<  8)
331 #define PIN_PA09D_SERCOM2_PAD1          _L_(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
332 #define MUX_PA09D_SERCOM2_PAD1          _L_(3)
333 #define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
334 #define PORT_PA09D_SERCOM2_PAD1  (_UL_(1) <<  9)
335 #define PIN_PA10D_SERCOM2_PAD2         _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
336 #define MUX_PA10D_SERCOM2_PAD2          _L_(3)
337 #define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
338 #define PORT_PA10D_SERCOM2_PAD2  (_UL_(1) << 10)
339 #define PIN_PA14C_SERCOM2_PAD2         _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
340 #define MUX_PA14C_SERCOM2_PAD2          _L_(2)
341 #define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
342 #define PORT_PA14C_SERCOM2_PAD2  (_UL_(1) << 14)
343 #define PIN_PA11D_SERCOM2_PAD3         _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
344 #define MUX_PA11D_SERCOM2_PAD3          _L_(3)
345 #define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
346 #define PORT_PA11D_SERCOM2_PAD3  (_UL_(1) << 11)
347 #define PIN_PA15C_SERCOM2_PAD3         _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
348 #define MUX_PA15C_SERCOM2_PAD3          _L_(2)
349 #define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
350 #define PORT_PA15C_SERCOM2_PAD3  (_UL_(1) << 15)
351 /* ========== PORT definition for SERCOM3 peripheral ========== */
352 #define PIN_PA16D_SERCOM3_PAD0         _L_(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
353 #define MUX_PA16D_SERCOM3_PAD0          _L_(3)
354 #define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
355 #define PORT_PA16D_SERCOM3_PAD0  (_UL_(1) << 16)
356 #define PIN_PA22C_SERCOM3_PAD0         _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
357 #define MUX_PA22C_SERCOM3_PAD0          _L_(2)
358 #define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
359 #define PORT_PA22C_SERCOM3_PAD0  (_UL_(1) << 22)
360 #define PIN_PA17D_SERCOM3_PAD1         _L_(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
361 #define MUX_PA17D_SERCOM3_PAD1          _L_(3)
362 #define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
363 #define PORT_PA17D_SERCOM3_PAD1  (_UL_(1) << 17)
364 #define PIN_PA23C_SERCOM3_PAD1         _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
365 #define MUX_PA23C_SERCOM3_PAD1          _L_(2)
366 #define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
367 #define PORT_PA23C_SERCOM3_PAD1  (_UL_(1) << 23)
368 #define PIN_PA18D_SERCOM3_PAD2         _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
369 #define MUX_PA18D_SERCOM3_PAD2          _L_(3)
370 #define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
371 #define PORT_PA18D_SERCOM3_PAD2  (_UL_(1) << 18)
372 #define PIN_PA24C_SERCOM3_PAD2         _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
373 #define MUX_PA24C_SERCOM3_PAD2          _L_(2)
374 #define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
375 #define PORT_PA24C_SERCOM3_PAD2  (_UL_(1) << 24)
376 #define PIN_PA19D_SERCOM3_PAD3         _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
377 #define MUX_PA19D_SERCOM3_PAD3          _L_(3)
378 #define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
379 #define PORT_PA19D_SERCOM3_PAD3  (_UL_(1) << 19)
380 #define PIN_PA25C_SERCOM3_PAD3         _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
381 #define MUX_PA25C_SERCOM3_PAD3          _L_(2)
382 #define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
383 #define PORT_PA25C_SERCOM3_PAD3  (_UL_(1) << 25)
384 /* ========== PORT definition for TC0 peripheral ========== */
385 #define PIN_PA04F_TC0_WO0               _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux F */
386 #define MUX_PA04F_TC0_WO0               _L_(5)
387 #define PINMUX_PA04F_TC0_WO0       ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)
388 #define PORT_PA04F_TC0_WO0     (_UL_(1) <<  4)
389 #define PIN_PA08E_TC0_WO0               _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */
390 #define MUX_PA08E_TC0_WO0               _L_(4)
391 #define PINMUX_PA08E_TC0_WO0       ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
392 #define PORT_PA08E_TC0_WO0     (_UL_(1) <<  8)
393 #define PIN_PA05F_TC0_WO1               _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux F */
394 #define MUX_PA05F_TC0_WO1               _L_(5)
395 #define PINMUX_PA05F_TC0_WO1       ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)
396 #define PORT_PA05F_TC0_WO1     (_UL_(1) <<  5)
397 #define PIN_PA09E_TC0_WO1               _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */
398 #define MUX_PA09E_TC0_WO1               _L_(4)
399 #define PINMUX_PA09E_TC0_WO1       ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
400 #define PORT_PA09E_TC0_WO1     (_UL_(1) <<  9)
401 /* ========== PORT definition for TC1 peripheral ========== */
402 #define PIN_PA06F_TC1_WO0               _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux F */
403 #define MUX_PA06F_TC1_WO0               _L_(5)
404 #define PINMUX_PA06F_TC1_WO0       ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)
405 #define PORT_PA06F_TC1_WO0     (_UL_(1) <<  6)
406 #define PIN_PA30F_TC1_WO0              _L_(30) /**< \brief TC1 signal: WO0 on PA30 mux F */
407 #define MUX_PA30F_TC1_WO0               _L_(5)
408 #define PINMUX_PA30F_TC1_WO0       ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)
409 #define PORT_PA30F_TC1_WO0     (_UL_(1) << 30)
410 #define PIN_PA10E_TC1_WO0              _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */
411 #define MUX_PA10E_TC1_WO0               _L_(4)
412 #define PINMUX_PA10E_TC1_WO0       ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
413 #define PORT_PA10E_TC1_WO0     (_UL_(1) << 10)
414 #define PIN_PA07F_TC1_WO1               _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux F */
415 #define MUX_PA07F_TC1_WO1               _L_(5)
416 #define PINMUX_PA07F_TC1_WO1       ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)
417 #define PORT_PA07F_TC1_WO1     (_UL_(1) <<  7)
418 #define PIN_PA31F_TC1_WO1              _L_(31) /**< \brief TC1 signal: WO1 on PA31 mux F */
419 #define MUX_PA31F_TC1_WO1               _L_(5)
420 #define PINMUX_PA31F_TC1_WO1       ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)
421 #define PORT_PA31F_TC1_WO1     (_UL_(1) << 31)
422 #define PIN_PA11E_TC1_WO1              _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */
423 #define MUX_PA11E_TC1_WO1               _L_(4)
424 #define PINMUX_PA11E_TC1_WO1       ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
425 #define PORT_PA11E_TC1_WO1     (_UL_(1) << 11)
426 /* ========== PORT definition for TC2 peripheral ========== */
427 #define PIN_PA16F_TC2_WO0              _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux F */
428 #define MUX_PA16F_TC2_WO0               _L_(5)
429 #define PINMUX_PA16F_TC2_WO0       ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)
430 #define PORT_PA16F_TC2_WO0     (_UL_(1) << 16)
431 #define PIN_PA00F_TC2_WO0               _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux F */
432 #define MUX_PA00F_TC2_WO0               _L_(5)
433 #define PINMUX_PA00F_TC2_WO0       ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)
434 #define PORT_PA00F_TC2_WO0     (_UL_(1) <<  0)
435 #define PIN_PA17F_TC2_WO1              _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux F */
436 #define MUX_PA17F_TC2_WO1               _L_(5)
437 #define PINMUX_PA17F_TC2_WO1       ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)
438 #define PORT_PA17F_TC2_WO1     (_UL_(1) << 17)
439 #define PIN_PA01F_TC2_WO1               _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux F */
440 #define MUX_PA01F_TC2_WO1               _L_(5)
441 #define PINMUX_PA01F_TC2_WO1       ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)
442 #define PORT_PA01F_TC2_WO1     (_UL_(1) <<  1)
443 /* ========== PORT definition for TC3 peripheral ========== */
444 #define PIN_PA18F_TC3_WO0              _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux F */
445 #define MUX_PA18F_TC3_WO0               _L_(5)
446 #define PINMUX_PA18F_TC3_WO0       ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)
447 #define PORT_PA18F_TC3_WO0     (_UL_(1) << 18)
448 #define PIN_PA14E_TC3_WO0              _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */
449 #define MUX_PA14E_TC3_WO0               _L_(4)
450 #define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
451 #define PORT_PA14E_TC3_WO0     (_UL_(1) << 14)
452 #define PIN_PA19F_TC3_WO1              _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux F */
453 #define MUX_PA19F_TC3_WO1               _L_(5)
454 #define PINMUX_PA19F_TC3_WO1       ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)
455 #define PORT_PA19F_TC3_WO1     (_UL_(1) << 19)
456 #define PIN_PA15E_TC3_WO1              _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */
457 #define MUX_PA15E_TC3_WO1               _L_(4)
458 #define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
459 #define PORT_PA15E_TC3_WO1     (_UL_(1) << 15)
460 /* ========== PORT definition for TC4 peripheral ========== */
461 #define PIN_PA22F_TC4_WO0              _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux F */
462 #define MUX_PA22F_TC4_WO0               _L_(5)
463 #define PINMUX_PA22F_TC4_WO0       ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)
464 #define PORT_PA22F_TC4_WO0     (_UL_(1) << 22)
465 #define PIN_PA23F_TC4_WO1              _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux F */
466 #define MUX_PA23F_TC4_WO1               _L_(5)
467 #define PINMUX_PA23F_TC4_WO1       ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)
468 #define PORT_PA23F_TC4_WO1     (_UL_(1) << 23)
469 /* ========== PORT definition for TC5 peripheral ========== */
470 #define PIN_PA24F_TC5_WO0              _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux F */
471 #define MUX_PA24F_TC5_WO0               _L_(5)
472 #define PINMUX_PA24F_TC5_WO0       ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)
473 #define PORT_PA24F_TC5_WO0     (_UL_(1) << 24)
474 #define PIN_PA25F_TC5_WO1              _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux F */
475 #define MUX_PA25F_TC5_WO1               _L_(5)
476 #define PINMUX_PA25F_TC5_WO1       ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)
477 #define PORT_PA25F_TC5_WO1     (_UL_(1) << 25)
478 /* ========== PORT definition for ADC peripheral ========== */
479 #define PIN_PA02B_ADC_AIN0              _L_(2) /**< \brief ADC signal: AIN0 on PA02 mux B */
480 #define MUX_PA02B_ADC_AIN0              _L_(1)
481 #define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
482 #define PORT_PA02B_ADC_AIN0    (_UL_(1) <<  2)
483 #define PIN_PA03B_ADC_AIN1              _L_(3) /**< \brief ADC signal: AIN1 on PA03 mux B */
484 #define MUX_PA03B_ADC_AIN1              _L_(1)
485 #define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
486 #define PORT_PA03B_ADC_AIN1    (_UL_(1) <<  3)
487 #define PIN_PA04B_ADC_AIN4              _L_(4) /**< \brief ADC signal: AIN4 on PA04 mux B */
488 #define MUX_PA04B_ADC_AIN4              _L_(1)
489 #define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
490 #define PORT_PA04B_ADC_AIN4    (_UL_(1) <<  4)
491 #define PIN_PA05B_ADC_AIN5              _L_(5) /**< \brief ADC signal: AIN5 on PA05 mux B */
492 #define MUX_PA05B_ADC_AIN5              _L_(1)
493 #define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
494 #define PORT_PA05B_ADC_AIN5    (_UL_(1) <<  5)
495 #define PIN_PA06B_ADC_AIN6              _L_(6) /**< \brief ADC signal: AIN6 on PA06 mux B */
496 #define MUX_PA06B_ADC_AIN6              _L_(1)
497 #define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
498 #define PORT_PA06B_ADC_AIN6    (_UL_(1) <<  6)
499 #define PIN_PA07B_ADC_AIN7              _L_(7) /**< \brief ADC signal: AIN7 on PA07 mux B */
500 #define MUX_PA07B_ADC_AIN7              _L_(1)
501 #define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
502 #define PORT_PA07B_ADC_AIN7    (_UL_(1) <<  7)
503 #define PIN_PA08B_ADC_AIN16             _L_(8) /**< \brief ADC signal: AIN16 on PA08 mux B */
504 #define MUX_PA08B_ADC_AIN16             _L_(1)
505 #define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
506 #define PORT_PA08B_ADC_AIN16   (_UL_(1) <<  8)
507 #define PIN_PA09B_ADC_AIN17             _L_(9) /**< \brief ADC signal: AIN17 on PA09 mux B */
508 #define MUX_PA09B_ADC_AIN17             _L_(1)
509 #define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
510 #define PORT_PA09B_ADC_AIN17   (_UL_(1) <<  9)
511 #define PIN_PA10B_ADC_AIN18            _L_(10) /**< \brief ADC signal: AIN18 on PA10 mux B */
512 #define MUX_PA10B_ADC_AIN18             _L_(1)
513 #define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
514 #define PORT_PA10B_ADC_AIN18   (_UL_(1) << 10)
515 #define PIN_PA11B_ADC_AIN19            _L_(11) /**< \brief ADC signal: AIN19 on PA11 mux B */
516 #define MUX_PA11B_ADC_AIN19             _L_(1)
517 #define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
518 #define PORT_PA11B_ADC_AIN19   (_UL_(1) << 11)
519 #define PIN_PA04B_ADC_VREFP             _L_(4) /**< \brief ADC signal: VREFP on PA04 mux B */
520 #define MUX_PA04B_ADC_VREFP             _L_(1)
521 #define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
522 #define PORT_PA04B_ADC_VREFP   (_UL_(1) <<  4)
523 /* ========== PORT definition for AC peripheral ========== */
524 #define PIN_PA04B_AC_AIN0               _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */
525 #define MUX_PA04B_AC_AIN0               _L_(1)
526 #define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
527 #define PORT_PA04B_AC_AIN0     (_UL_(1) <<  4)
528 #define PIN_PA05B_AC_AIN1               _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */
529 #define MUX_PA05B_AC_AIN1               _L_(1)
530 #define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
531 #define PORT_PA05B_AC_AIN1     (_UL_(1) <<  5)
532 #define PIN_PA06B_AC_AIN2               _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */
533 #define MUX_PA06B_AC_AIN2               _L_(1)
534 #define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
535 #define PORT_PA06B_AC_AIN2     (_UL_(1) <<  6)
536 #define PIN_PA07B_AC_AIN3               _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */
537 #define MUX_PA07B_AC_AIN3               _L_(1)
538 #define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
539 #define PORT_PA07B_AC_AIN3     (_UL_(1) <<  7)
540 #define PIN_PA18H_AC_CMP0              _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */
541 #define MUX_PA18H_AC_CMP0               _L_(7)
542 #define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
543 #define PORT_PA18H_AC_CMP0     (_UL_(1) << 18)
544 #define PIN_PA19H_AC_CMP1              _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */
545 #define MUX_PA19H_AC_CMP1               _L_(7)
546 #define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
547 #define PORT_PA19H_AC_CMP1     (_UL_(1) << 19)
548 /* ========== PORT definition for DAC peripheral ========== */
549 #define PIN_PA02B_DAC_VOUT              _L_(2) /**< \brief DAC signal: VOUT on PA02 mux B */
550 #define MUX_PA02B_DAC_VOUT              _L_(1)
551 #define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
552 #define PORT_PA02B_DAC_VOUT    (_UL_(1) <<  2)
553 #define PIN_PA03B_DAC_VREFP             _L_(3) /**< \brief DAC signal: VREFP on PA03 mux B */
554 #define MUX_PA03B_DAC_VREFP             _L_(1)
555 #define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
556 #define PORT_PA03B_DAC_VREFP   (_UL_(1) <<  3)
557 
558 #endif /* _SAMD20E16_PIO_ */
559