1 /** 2 * \file 3 * 4 * \brief Peripheral I/O description for SAMR21E17A 5 * 6 * Copyright (c) 2017 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAMR21E17A_PIO_ 30 #define _SAMR21E17A_PIO_ 31 32 #define PIN_PA06 6 /**< \brief Pin Number for PA06 */ 33 #define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ 34 #define PIN_PA07 7 /**< \brief Pin Number for PA07 */ 35 #define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ 36 #define PIN_PA08 8 /**< \brief Pin Number for PA08 */ 37 #define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ 38 #define PIN_PA09 9 /**< \brief Pin Number for PA09 */ 39 #define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ 40 #define PIN_PA10 10 /**< \brief Pin Number for PA10 */ 41 #define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ 42 #define PIN_PA11 11 /**< \brief Pin Number for PA11 */ 43 #define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ 44 #define PIN_PA14 14 /**< \brief Pin Number for PA14 */ 45 #define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ 46 #define PIN_PA15 15 /**< \brief Pin Number for PA15 */ 47 #define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ 48 #define PIN_PA16 16 /**< \brief Pin Number for PA16 */ 49 #define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ 50 #define PIN_PA17 17 /**< \brief Pin Number for PA17 */ 51 #define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ 52 #define PIN_PA18 18 /**< \brief Pin Number for PA18 */ 53 #define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ 54 #define PIN_PA19 19 /**< \brief Pin Number for PA19 */ 55 #define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ 56 #define PIN_PA20 20 /**< \brief Pin Number for PA20 */ 57 #define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ 58 #define PIN_PA24 24 /**< \brief Pin Number for PA24 */ 59 #define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ 60 #define PIN_PA25 25 /**< \brief Pin Number for PA25 */ 61 #define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ 62 #define PIN_PA27 27 /**< \brief Pin Number for PA27 */ 63 #define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ 64 #define PIN_PA28 28 /**< \brief Pin Number for PA28 */ 65 #define PORT_PA28 (_UL_(1) << 28) /**< \brief PORT Mask for PA28 */ 66 #define PIN_PA30 30 /**< \brief Pin Number for PA30 */ 67 #define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ 68 #define PIN_PA31 31 /**< \brief Pin Number for PA31 */ 69 #define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ 70 #define PIN_PB00 32 /**< \brief Pin Number for PB00 */ 71 #define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ 72 #define PIN_PB08 40 /**< \brief Pin Number for PB08 */ 73 #define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ 74 #define PIN_PB09 41 /**< \brief Pin Number for PB09 */ 75 #define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ 76 #define PIN_PB14 46 /**< \brief Pin Number for PB14 */ 77 #define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ 78 #define PIN_PB15 47 /**< \brief Pin Number for PB15 */ 79 #define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ 80 #define PIN_PB16 48 /**< \brief Pin Number for PB16 */ 81 #define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ 82 #define PIN_PB17 49 /**< \brief Pin Number for PB17 */ 83 #define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ 84 #define PIN_PB30 62 /**< \brief Pin Number for PB30 */ 85 #define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ 86 #define PIN_PB31 63 /**< \brief Pin Number for PB31 */ 87 #define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ 88 #define PIN_PC16 80 /**< \brief Pin Number for PC16 */ 89 #define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ 90 #define PIN_PC18 82 /**< \brief Pin Number for PC18 */ 91 #define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ 92 #define PIN_PC19 83 /**< \brief Pin Number for PC19 */ 93 #define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ 94 /* ========== PORT definition for GCLK peripheral ========== */ 95 #define PIN_PB14H_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux H */ 96 #define MUX_PB14H_GCLK_IO0 _L_(7) 97 #define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) 98 #define PORT_PB14H_GCLK_IO0 (_UL_(1) << 14) 99 #define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ 100 #define MUX_PA14H_GCLK_IO0 _L_(7) 101 #define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) 102 #define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) 103 #define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ 104 #define MUX_PA27H_GCLK_IO0 _L_(7) 105 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) 106 #define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) 107 #define PIN_PA28H_GCLK_IO0 _L_(28) /**< \brief GCLK signal: IO0 on PA28 mux H */ 108 #define MUX_PA28H_GCLK_IO0 _L_(7) 109 #define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) 110 #define PORT_PA28H_GCLK_IO0 (_UL_(1) << 28) 111 #define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ 112 #define MUX_PA30H_GCLK_IO0 _L_(7) 113 #define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) 114 #define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) 115 #define PIN_PB15H_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux H */ 116 #define MUX_PB15H_GCLK_IO1 _L_(7) 117 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) 118 #define PORT_PB15H_GCLK_IO1 (_UL_(1) << 15) 119 #define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ 120 #define MUX_PA15H_GCLK_IO1 _L_(7) 121 #define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) 122 #define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) 123 #define PIN_PC16F_GCLK_IO1 _L_(80) /**< \brief GCLK signal: IO1 on PC16 mux F */ 124 #define MUX_PC16F_GCLK_IO1 _L_(5) 125 #define PINMUX_PC16F_GCLK_IO1 ((PIN_PC16F_GCLK_IO1 << 16) | MUX_PC16F_GCLK_IO1) 126 #define PORT_PC16F_GCLK_IO1 (_UL_(1) << 16) 127 #define PIN_PB16H_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux H */ 128 #define MUX_PB16H_GCLK_IO2 _L_(7) 129 #define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) 130 #define PORT_PB16H_GCLK_IO2 (_UL_(1) << 16) 131 #define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ 132 #define MUX_PA16H_GCLK_IO2 _L_(7) 133 #define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) 134 #define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) 135 #define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ 136 #define MUX_PA17H_GCLK_IO3 _L_(7) 137 #define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) 138 #define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) 139 #define PIN_PB17H_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux H */ 140 #define MUX_PB17H_GCLK_IO3 _L_(7) 141 #define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) 142 #define PORT_PB17H_GCLK_IO3 (_UL_(1) << 17) 143 #define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ 144 #define MUX_PA10H_GCLK_IO4 _L_(7) 145 #define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) 146 #define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) 147 #define PIN_PA20H_GCLK_IO4 _L_(20) /**< \brief GCLK signal: IO4 on PA20 mux H */ 148 #define MUX_PA20H_GCLK_IO4 _L_(7) 149 #define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) 150 #define PORT_PA20H_GCLK_IO4 (_UL_(1) << 20) 151 #define PIN_PA11H_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux H */ 152 #define MUX_PA11H_GCLK_IO5 _L_(7) 153 #define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) 154 #define PORT_PA11H_GCLK_IO5 (_UL_(1) << 11) 155 /* ========== PORT definition for EIC peripheral ========== */ 156 #define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ 157 #define MUX_PA16A_EIC_EXTINT0 _L_(0) 158 #define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) 159 #define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) 160 #define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ 161 #define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ 162 #define MUX_PB00A_EIC_EXTINT0 _L_(0) 163 #define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) 164 #define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) 165 #define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ 166 #define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ 167 #define MUX_PB16A_EIC_EXTINT0 _L_(0) 168 #define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) 169 #define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) 170 #define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ 171 #define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ 172 #define MUX_PA17A_EIC_EXTINT1 _L_(0) 173 #define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) 174 #define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) 175 #define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ 176 #define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ 177 #define MUX_PB17A_EIC_EXTINT1 _L_(0) 178 #define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) 179 #define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) 180 #define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ 181 #define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ 182 #define MUX_PA18A_EIC_EXTINT2 _L_(0) 183 #define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) 184 #define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) 185 #define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ 186 #define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ 187 #define MUX_PA19A_EIC_EXTINT3 _L_(0) 188 #define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) 189 #define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) 190 #define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ 191 #define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ 192 #define MUX_PA20A_EIC_EXTINT4 _L_(0) 193 #define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) 194 #define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) 195 #define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ 196 #define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ 197 #define MUX_PA06A_EIC_EXTINT6 _L_(0) 198 #define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) 199 #define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) 200 #define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ 201 #define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ 202 #define MUX_PA07A_EIC_EXTINT7 _L_(0) 203 #define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) 204 #define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) 205 #define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ 206 #define PIN_PA28A_EIC_EXTINT8 _L_(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */ 207 #define MUX_PA28A_EIC_EXTINT8 _L_(0) 208 #define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) 209 #define PORT_PA28A_EIC_EXTINT8 (_UL_(1) << 28) 210 #define PIN_PA28A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */ 211 #define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ 212 #define MUX_PB08A_EIC_EXTINT8 _L_(0) 213 #define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) 214 #define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) 215 #define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ 216 #define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ 217 #define MUX_PA09A_EIC_EXTINT9 _L_(0) 218 #define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) 219 #define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) 220 #define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ 221 #define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ 222 #define MUX_PB09A_EIC_EXTINT9 _L_(0) 223 #define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) 224 #define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) 225 #define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ 226 #define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ 227 #define MUX_PA10A_EIC_EXTINT10 _L_(0) 228 #define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) 229 #define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) 230 #define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ 231 #define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ 232 #define MUX_PA30A_EIC_EXTINT10 _L_(0) 233 #define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) 234 #define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) 235 #define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ 236 #define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ 237 #define MUX_PA11A_EIC_EXTINT11 _L_(0) 238 #define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) 239 #define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) 240 #define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ 241 #define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ 242 #define MUX_PA31A_EIC_EXTINT11 _L_(0) 243 #define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) 244 #define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) 245 #define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ 246 #define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ 247 #define MUX_PA24A_EIC_EXTINT12 _L_(0) 248 #define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) 249 #define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) 250 #define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ 251 #define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ 252 #define MUX_PA25A_EIC_EXTINT13 _L_(0) 253 #define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) 254 #define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) 255 #define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ 256 #define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ 257 #define MUX_PB14A_EIC_EXTINT14 _L_(0) 258 #define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) 259 #define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) 260 #define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ 261 #define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ 262 #define MUX_PB30A_EIC_EXTINT14 _L_(0) 263 #define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) 264 #define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) 265 #define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ 266 #define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ 267 #define MUX_PA14A_EIC_EXTINT14 _L_(0) 268 #define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) 269 #define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) 270 #define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ 271 #define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ 272 #define MUX_PA15A_EIC_EXTINT15 _L_(0) 273 #define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) 274 #define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) 275 #define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ 276 #define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ 277 #define MUX_PA27A_EIC_EXTINT15 _L_(0) 278 #define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) 279 #define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) 280 #define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ 281 #define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ 282 #define MUX_PB15A_EIC_EXTINT15 _L_(0) 283 #define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) 284 #define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) 285 #define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ 286 #define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ 287 #define MUX_PB31A_EIC_EXTINT15 _L_(0) 288 #define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) 289 #define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) 290 #define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ 291 #define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ 292 #define MUX_PA08A_EIC_NMI _L_(0) 293 #define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) 294 #define PORT_PA08A_EIC_NMI (_UL_(1) << 8) 295 /* ========== PORT definition for USB peripheral ========== */ 296 #define PIN_PA24G_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux G */ 297 #define MUX_PA24G_USB_DM _L_(6) 298 #define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) 299 #define PORT_PA24G_USB_DM (_UL_(1) << 24) 300 #define PIN_PA25G_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux G */ 301 #define MUX_PA25G_USB_DP _L_(6) 302 #define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) 303 #define PORT_PA25G_USB_DP (_UL_(1) << 25) 304 /* ========== PORT definition for SERCOM0 peripheral ========== */ 305 #define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ 306 #define MUX_PA08C_SERCOM0_PAD0 _L_(2) 307 #define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) 308 #define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) 309 #define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ 310 #define MUX_PA09C_SERCOM0_PAD1 _L_(2) 311 #define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) 312 #define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) 313 #define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ 314 #define MUX_PA06D_SERCOM0_PAD2 _L_(3) 315 #define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) 316 #define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) 317 #define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ 318 #define MUX_PA10C_SERCOM0_PAD2 _L_(2) 319 #define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) 320 #define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) 321 #define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ 322 #define MUX_PA07D_SERCOM0_PAD3 _L_(3) 323 #define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) 324 #define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) 325 #define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ 326 #define MUX_PA11C_SERCOM0_PAD3 _L_(2) 327 #define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) 328 #define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) 329 /* ========== PORT definition for SERCOM1 peripheral ========== */ 330 #define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ 331 #define MUX_PA16C_SERCOM1_PAD0 _L_(2) 332 #define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) 333 #define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) 334 #define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ 335 #define MUX_PA17C_SERCOM1_PAD1 _L_(2) 336 #define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) 337 #define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) 338 #define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ 339 #define MUX_PA30D_SERCOM1_PAD2 _L_(3) 340 #define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) 341 #define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) 342 #define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ 343 #define MUX_PA18C_SERCOM1_PAD2 _L_(2) 344 #define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) 345 #define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) 346 #define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ 347 #define MUX_PA31D_SERCOM1_PAD3 _L_(3) 348 #define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) 349 #define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) 350 #define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ 351 #define MUX_PA19C_SERCOM1_PAD3 _L_(2) 352 #define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) 353 #define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) 354 /* ========== PORT definition for SERCOM2 peripheral ========== */ 355 #define PIN_PA08D_SERCOM2_PAD0 _L_(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ 356 #define MUX_PA08D_SERCOM2_PAD0 _L_(3) 357 #define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) 358 #define PORT_PA08D_SERCOM2_PAD0 (_UL_(1) << 8) 359 #define PIN_PA09D_SERCOM2_PAD1 _L_(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ 360 #define MUX_PA09D_SERCOM2_PAD1 _L_(3) 361 #define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) 362 #define PORT_PA09D_SERCOM2_PAD1 (_UL_(1) << 9) 363 #define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ 364 #define MUX_PA10D_SERCOM2_PAD2 _L_(3) 365 #define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) 366 #define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) 367 #define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ 368 #define MUX_PA14C_SERCOM2_PAD2 _L_(2) 369 #define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) 370 #define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) 371 #define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ 372 #define MUX_PA11D_SERCOM2_PAD3 _L_(3) 373 #define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) 374 #define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) 375 #define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ 376 #define MUX_PA15C_SERCOM2_PAD3 _L_(2) 377 #define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) 378 #define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) 379 /* ========== PORT definition for SERCOM3 peripheral ========== */ 380 #define PIN_PA16D_SERCOM3_PAD0 _L_(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ 381 #define MUX_PA16D_SERCOM3_PAD0 _L_(3) 382 #define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) 383 #define PORT_PA16D_SERCOM3_PAD0 (_UL_(1) << 16) 384 #define PIN_PA27F_SERCOM3_PAD0 _L_(27) /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */ 385 #define MUX_PA27F_SERCOM3_PAD0 _L_(5) 386 #define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0) 387 #define PORT_PA27F_SERCOM3_PAD0 (_UL_(1) << 27) 388 #define PIN_PA17D_SERCOM3_PAD1 _L_(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ 389 #define MUX_PA17D_SERCOM3_PAD1 _L_(3) 390 #define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) 391 #define PORT_PA17D_SERCOM3_PAD1 (_UL_(1) << 17) 392 #define PIN_PA28F_SERCOM3_PAD1 _L_(28) /**< \brief SERCOM3 signal: PAD1 on PA28 mux F */ 393 #define MUX_PA28F_SERCOM3_PAD1 _L_(5) 394 #define PINMUX_PA28F_SERCOM3_PAD1 ((PIN_PA28F_SERCOM3_PAD1 << 16) | MUX_PA28F_SERCOM3_PAD1) 395 #define PORT_PA28F_SERCOM3_PAD1 (_UL_(1) << 28) 396 #define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ 397 #define MUX_PA18D_SERCOM3_PAD2 _L_(3) 398 #define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) 399 #define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) 400 #define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ 401 #define MUX_PA20D_SERCOM3_PAD2 _L_(3) 402 #define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) 403 #define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) 404 #define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ 405 #define MUX_PA24C_SERCOM3_PAD2 _L_(2) 406 #define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) 407 #define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) 408 #define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ 409 #define MUX_PA19D_SERCOM3_PAD3 _L_(3) 410 #define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) 411 #define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) 412 #define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ 413 #define MUX_PA25C_SERCOM3_PAD3 _L_(2) 414 #define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) 415 #define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) 416 /* ========== PORT definition for SERCOM4 peripheral ========== */ 417 #define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ 418 #define MUX_PB08D_SERCOM4_PAD0 _L_(3) 419 #define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) 420 #define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) 421 #define PIN_PC19F_SERCOM4_PAD0 _L_(83) /**< \brief SERCOM4 signal: PAD0 on PC19 mux F */ 422 #define MUX_PC19F_SERCOM4_PAD0 _L_(5) 423 #define PINMUX_PC19F_SERCOM4_PAD0 ((PIN_PC19F_SERCOM4_PAD0 << 16) | MUX_PC19F_SERCOM4_PAD0) 424 #define PORT_PC19F_SERCOM4_PAD0 (_UL_(1) << 19) 425 #define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ 426 #define MUX_PB09D_SERCOM4_PAD1 _L_(3) 427 #define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) 428 #define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) 429 #define PIN_PB31F_SERCOM4_PAD1 _L_(63) /**< \brief SERCOM4 signal: PAD1 on PB31 mux F */ 430 #define MUX_PB31F_SERCOM4_PAD1 _L_(5) 431 #define PINMUX_PB31F_SERCOM4_PAD1 ((PIN_PB31F_SERCOM4_PAD1 << 16) | MUX_PB31F_SERCOM4_PAD1) 432 #define PORT_PB31F_SERCOM4_PAD1 (_UL_(1) << 31) 433 #define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ 434 #define MUX_PA14D_SERCOM4_PAD2 _L_(3) 435 #define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) 436 #define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) 437 #define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ 438 #define MUX_PB14C_SERCOM4_PAD2 _L_(2) 439 #define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) 440 #define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) 441 #define PIN_PB30F_SERCOM4_PAD2 _L_(62) /**< \brief SERCOM4 signal: PAD2 on PB30 mux F */ 442 #define MUX_PB30F_SERCOM4_PAD2 _L_(5) 443 #define PINMUX_PB30F_SERCOM4_PAD2 ((PIN_PB30F_SERCOM4_PAD2 << 16) | MUX_PB30F_SERCOM4_PAD2) 444 #define PORT_PB30F_SERCOM4_PAD2 (_UL_(1) << 30) 445 #define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ 446 #define MUX_PA15D_SERCOM4_PAD3 _L_(3) 447 #define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) 448 #define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) 449 #define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ 450 #define MUX_PB15C_SERCOM4_PAD3 _L_(2) 451 #define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) 452 #define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) 453 #define PIN_PC18F_SERCOM4_PAD3 _L_(82) /**< \brief SERCOM4 signal: PAD3 on PC18 mux F */ 454 #define MUX_PC18F_SERCOM4_PAD3 _L_(5) 455 #define PINMUX_PC18F_SERCOM4_PAD3 ((PIN_PC18F_SERCOM4_PAD3 << 16) | MUX_PC18F_SERCOM4_PAD3) 456 #define PORT_PC18F_SERCOM4_PAD3 (_UL_(1) << 18) 457 /* ========== PORT definition for SERCOM5 peripheral ========== */ 458 #define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ 459 #define MUX_PB16C_SERCOM5_PAD0 _L_(2) 460 #define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) 461 #define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) 462 #define PIN_PB30D_SERCOM5_PAD0 _L_(62) /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ 463 #define MUX_PB30D_SERCOM5_PAD0 _L_(3) 464 #define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) 465 #define PORT_PB30D_SERCOM5_PAD0 (_UL_(1) << 30) 466 #define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ 467 #define MUX_PB17C_SERCOM5_PAD1 _L_(2) 468 #define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) 469 #define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) 470 #define PIN_PB31D_SERCOM5_PAD1 _L_(63) /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ 471 #define MUX_PB31D_SERCOM5_PAD1 _L_(3) 472 #define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) 473 #define PORT_PB31D_SERCOM5_PAD1 (_UL_(1) << 31) 474 #define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ 475 #define MUX_PA24D_SERCOM5_PAD2 _L_(3) 476 #define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) 477 #define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) 478 #define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ 479 #define MUX_PB00D_SERCOM5_PAD2 _L_(3) 480 #define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) 481 #define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) 482 #define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ 483 #define MUX_PA20C_SERCOM5_PAD2 _L_(2) 484 #define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) 485 #define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) 486 #define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ 487 #define MUX_PA25D_SERCOM5_PAD3 _L_(3) 488 #define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) 489 #define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) 490 /* ========== PORT definition for TCC0 peripheral ========== */ 491 #define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ 492 #define MUX_PA08E_TCC0_WO0 _L_(4) 493 #define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) 494 #define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8) 495 #define PIN_PB30E_TCC0_WO0 _L_(62) /**< \brief TCC0 signal: WO0 on PB30 mux E */ 496 #define MUX_PB30E_TCC0_WO0 _L_(4) 497 #define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) 498 #define PORT_PB30E_TCC0_WO0 (_UL_(1) << 30) 499 #define PIN_PA16F_TCC0_WO0 _L_(16) /**< \brief TCC0 signal: WO0 on PA16 mux F */ 500 #define MUX_PA16F_TCC0_WO0 _L_(5) 501 #define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0) 502 #define PORT_PA16F_TCC0_WO0 (_UL_(1) << 16) 503 #define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ 504 #define MUX_PA09E_TCC0_WO1 _L_(4) 505 #define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) 506 #define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9) 507 #define PIN_PB31E_TCC0_WO1 _L_(63) /**< \brief TCC0 signal: WO1 on PB31 mux E */ 508 #define MUX_PB31E_TCC0_WO1 _L_(4) 509 #define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) 510 #define PORT_PB31E_TCC0_WO1 (_UL_(1) << 31) 511 #define PIN_PA17F_TCC0_WO1 _L_(17) /**< \brief TCC0 signal: WO1 on PA17 mux F */ 512 #define MUX_PA17F_TCC0_WO1 _L_(5) 513 #define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1) 514 #define PORT_PA17F_TCC0_WO1 (_UL_(1) << 17) 515 #define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ 516 #define MUX_PA10F_TCC0_WO2 _L_(5) 517 #define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) 518 #define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) 519 #define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ 520 #define MUX_PA18F_TCC0_WO2 _L_(5) 521 #define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) 522 #define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18) 523 #define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ 524 #define MUX_PA11F_TCC0_WO3 _L_(5) 525 #define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) 526 #define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) 527 #define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ 528 #define MUX_PA19F_TCC0_WO3 _L_(5) 529 #define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) 530 #define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19) 531 #define PIN_PB16F_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux F */ 532 #define MUX_PB16F_TCC0_WO4 _L_(5) 533 #define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) 534 #define PORT_PB16F_TCC0_WO4 (_UL_(1) << 16) 535 #define PIN_PB17F_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux F */ 536 #define MUX_PB17F_TCC0_WO5 _L_(5) 537 #define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) 538 #define PORT_PB17F_TCC0_WO5 (_UL_(1) << 17) 539 #define PIN_PA20F_TCC0_WO6 _L_(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */ 540 #define MUX_PA20F_TCC0_WO6 _L_(5) 541 #define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) 542 #define PORT_PA20F_TCC0_WO6 (_UL_(1) << 20) 543 /* ========== PORT definition for TCC1 peripheral ========== */ 544 #define PIN_PA06E_TCC1_WO0 _L_(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */ 545 #define MUX_PA06E_TCC1_WO0 _L_(4) 546 #define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) 547 #define PORT_PA06E_TCC1_WO0 (_UL_(1) << 6) 548 #define PIN_PA10E_TCC1_WO0 _L_(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */ 549 #define MUX_PA10E_TCC1_WO0 _L_(4) 550 #define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) 551 #define PORT_PA10E_TCC1_WO0 (_UL_(1) << 10) 552 #define PIN_PA30E_TCC1_WO0 _L_(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */ 553 #define MUX_PA30E_TCC1_WO0 _L_(4) 554 #define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) 555 #define PORT_PA30E_TCC1_WO0 (_UL_(1) << 30) 556 #define PIN_PA07E_TCC1_WO1 _L_(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */ 557 #define MUX_PA07E_TCC1_WO1 _L_(4) 558 #define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) 559 #define PORT_PA07E_TCC1_WO1 (_UL_(1) << 7) 560 #define PIN_PA11E_TCC1_WO1 _L_(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */ 561 #define MUX_PA11E_TCC1_WO1 _L_(4) 562 #define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) 563 #define PORT_PA11E_TCC1_WO1 (_UL_(1) << 11) 564 #define PIN_PA31E_TCC1_WO1 _L_(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */ 565 #define MUX_PA31E_TCC1_WO1 _L_(4) 566 #define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) 567 #define PORT_PA31E_TCC1_WO1 (_UL_(1) << 31) 568 #define PIN_PA24F_TCC1_WO2 _L_(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */ 569 #define MUX_PA24F_TCC1_WO2 _L_(5) 570 #define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) 571 #define PORT_PA24F_TCC1_WO2 (_UL_(1) << 24) 572 #define PIN_PA25F_TCC1_WO3 _L_(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */ 573 #define MUX_PA25F_TCC1_WO3 _L_(5) 574 #define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) 575 #define PORT_PA25F_TCC1_WO3 (_UL_(1) << 25) 576 /* ========== PORT definition for TCC2 peripheral ========== */ 577 #define PIN_PA16E_TCC2_WO0 _L_(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */ 578 #define MUX_PA16E_TCC2_WO0 _L_(4) 579 #define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) 580 #define PORT_PA16E_TCC2_WO0 (_UL_(1) << 16) 581 #define PIN_PA17E_TCC2_WO1 _L_(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */ 582 #define MUX_PA17E_TCC2_WO1 _L_(4) 583 #define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) 584 #define PORT_PA17E_TCC2_WO1 (_UL_(1) << 17) 585 /* ========== PORT definition for TC3 peripheral ========== */ 586 #define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ 587 #define MUX_PA18E_TC3_WO0 _L_(4) 588 #define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) 589 #define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) 590 #define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ 591 #define MUX_PA14E_TC3_WO0 _L_(4) 592 #define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) 593 #define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) 594 #define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ 595 #define MUX_PA19E_TC3_WO1 _L_(4) 596 #define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) 597 #define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) 598 #define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ 599 #define MUX_PA15E_TC3_WO1 _L_(4) 600 #define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) 601 #define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) 602 /* ========== PORT definition for TC4 peripheral ========== */ 603 #define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ 604 #define MUX_PB08E_TC4_WO0 _L_(4) 605 #define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) 606 #define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) 607 #define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ 608 #define MUX_PB09E_TC4_WO1 _L_(4) 609 #define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) 610 #define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) 611 /* ========== PORT definition for TC5 peripheral ========== */ 612 #define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ 613 #define MUX_PA24E_TC5_WO0 _L_(4) 614 #define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) 615 #define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) 616 #define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ 617 #define MUX_PB14E_TC5_WO0 _L_(4) 618 #define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) 619 #define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) 620 #define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ 621 #define MUX_PA25E_TC5_WO1 _L_(4) 622 #define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) 623 #define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) 624 #define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ 625 #define MUX_PB15E_TC5_WO1 _L_(4) 626 #define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) 627 #define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) 628 /* ========== PORT definition for TC6 peripheral ========== */ 629 #define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ 630 #define MUX_PB16E_TC6_WO0 _L_(4) 631 #define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) 632 #define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) 633 #define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ 634 #define MUX_PB17E_TC6_WO1 _L_(4) 635 #define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) 636 #define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) 637 /* ========== PORT definition for TC7 peripheral ========== */ 638 #define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ 639 #define MUX_PA20E_TC7_WO0 _L_(4) 640 #define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) 641 #define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) 642 #define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ 643 #define MUX_PB00E_TC7_WO0 _L_(4) 644 #define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) 645 #define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) 646 /* ========== PORT definition for ADC peripheral ========== */ 647 #define PIN_PB08B_ADC_AIN2 _L_(40) /**< \brief ADC signal: AIN2 on PB08 mux B */ 648 #define MUX_PB08B_ADC_AIN2 _L_(1) 649 #define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) 650 #define PORT_PB08B_ADC_AIN2 (_UL_(1) << 8) 651 #define PIN_PB09B_ADC_AIN3 _L_(41) /**< \brief ADC signal: AIN3 on PB09 mux B */ 652 #define MUX_PB09B_ADC_AIN3 _L_(1) 653 #define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) 654 #define PORT_PB09B_ADC_AIN3 (_UL_(1) << 9) 655 #define PIN_PA06B_ADC_AIN6 _L_(6) /**< \brief ADC signal: AIN6 on PA06 mux B */ 656 #define MUX_PA06B_ADC_AIN6 _L_(1) 657 #define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) 658 #define PORT_PA06B_ADC_AIN6 (_UL_(1) << 6) 659 #define PIN_PA07B_ADC_AIN7 _L_(7) /**< \brief ADC signal: AIN7 on PA07 mux B */ 660 #define MUX_PA07B_ADC_AIN7 _L_(1) 661 #define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) 662 #define PORT_PA07B_ADC_AIN7 (_UL_(1) << 7) 663 #define PIN_PB00B_ADC_AIN8 _L_(32) /**< \brief ADC signal: AIN8 on PB00 mux B */ 664 #define MUX_PB00B_ADC_AIN8 _L_(1) 665 #define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) 666 #define PORT_PB00B_ADC_AIN8 (_UL_(1) << 0) 667 #define PIN_PA08B_ADC_AIN16 _L_(8) /**< \brief ADC signal: AIN16 on PA08 mux B */ 668 #define MUX_PA08B_ADC_AIN16 _L_(1) 669 #define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) 670 #define PORT_PA08B_ADC_AIN16 (_UL_(1) << 8) 671 #define PIN_PA09B_ADC_AIN17 _L_(9) /**< \brief ADC signal: AIN17 on PA09 mux B */ 672 #define MUX_PA09B_ADC_AIN17 _L_(1) 673 #define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) 674 #define PORT_PA09B_ADC_AIN17 (_UL_(1) << 9) 675 #define PIN_PA10B_ADC_AIN18 _L_(10) /**< \brief ADC signal: AIN18 on PA10 mux B */ 676 #define MUX_PA10B_ADC_AIN18 _L_(1) 677 #define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) 678 #define PORT_PA10B_ADC_AIN18 (_UL_(1) << 10) 679 #define PIN_PA11B_ADC_AIN19 _L_(11) /**< \brief ADC signal: AIN19 on PA11 mux B */ 680 #define MUX_PA11B_ADC_AIN19 _L_(1) 681 #define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) 682 #define PORT_PA11B_ADC_AIN19 (_UL_(1) << 11) 683 /* ========== PORT definition for AC peripheral ========== */ 684 #define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ 685 #define MUX_PA06B_AC_AIN2 _L_(1) 686 #define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) 687 #define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) 688 #define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ 689 #define MUX_PA07B_AC_AIN3 _L_(1) 690 #define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) 691 #define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) 692 #define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ 693 #define MUX_PA18H_AC_CMP0 _L_(7) 694 #define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) 695 #define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) 696 #define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ 697 #define MUX_PA19H_AC_CMP1 _L_(7) 698 #define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) 699 #define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) 700 /* ========== PORT definition for RFCTRL peripheral ========== */ 701 #define PIN_PA08F_RFCTRL_FECTRL0 _L_(8) /**< \brief RFCTRL signal: FECTRL0 on PA08 mux F */ 702 #define MUX_PA08F_RFCTRL_FECTRL0 _L_(5) 703 #define PINMUX_PA08F_RFCTRL_FECTRL0 ((PIN_PA08F_RFCTRL_FECTRL0 << 16) | MUX_PA08F_RFCTRL_FECTRL0) 704 #define PORT_PA08F_RFCTRL_FECTRL0 (_UL_(1) << 8) 705 #define PIN_PA09F_RFCTRL_FECTRL1 _L_(9) /**< \brief RFCTRL signal: FECTRL1 on PA09 mux F */ 706 #define MUX_PA09F_RFCTRL_FECTRL1 _L_(5) 707 #define PINMUX_PA09F_RFCTRL_FECTRL1 ((PIN_PA09F_RFCTRL_FECTRL1 << 16) | MUX_PA09F_RFCTRL_FECTRL1) 708 #define PORT_PA09F_RFCTRL_FECTRL1 (_UL_(1) << 9) 709 #define PIN_PA14F_RFCTRL_FECTRL4 _L_(14) /**< \brief RFCTRL signal: FECTRL4 on PA14 mux F */ 710 #define MUX_PA14F_RFCTRL_FECTRL4 _L_(5) 711 #define PINMUX_PA14F_RFCTRL_FECTRL4 ((PIN_PA14F_RFCTRL_FECTRL4 << 16) | MUX_PA14F_RFCTRL_FECTRL4) 712 #define PORT_PA14F_RFCTRL_FECTRL4 (_UL_(1) << 14) 713 #define PIN_PA15F_RFCTRL_FECTRL5 _L_(15) /**< \brief RFCTRL signal: FECTRL5 on PA15 mux F */ 714 #define MUX_PA15F_RFCTRL_FECTRL5 _L_(5) 715 #define PINMUX_PA15F_RFCTRL_FECTRL5 ((PIN_PA15F_RFCTRL_FECTRL5 << 16) | MUX_PA15F_RFCTRL_FECTRL5) 716 #define PORT_PA15F_RFCTRL_FECTRL5 (_UL_(1) << 15) 717 718 #endif /* _SAMR21E17A_PIO_ */ 719
