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Searched refs:CSSELR (Results 1 – 8 of 8) sorted by relevance

/cmsis_6-latest/CMSIS/Core/Include/m-profile/
Darmv7m_cachel1.h148 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_EnableDCache()
192 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_DisableDCache()
254 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_InvalidateDCache()
289 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_CleanDCache()
324 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_CleanInvalidateDCache()
/cmsis_6-latest/CMSIS/Core/Include/
Dcore_starmc1.h557 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
3252 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_EnableDCache()
3290 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_DisableDCache()
3328 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_InvalidateDCache()
3363 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_CleanDCache()
3398 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_CleanInvalidateDCache()
Dcore_cm7.h493 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
Dcore_cm33.h545 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
Dcore_cm35p.h545 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
Dcore_cm52.h581 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
Dcore_cm55.h555 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
Dcore_cm85.h576 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member