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Searched refs:__ROM0_BASE (Results 1 – 25 of 40) sorted by relevance

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/cmsis-dsp-latest/dsppp/RTE/Device/SSE_300_MPS3/
Dac6_linker_script.sct32 LR_ROM0 __ROM0_BASE __ROM0_SIZE {
35 ER_CMSE_VENEER __ROM0_BASE+__ROM0_SIZE -__ROM0_SIZE {
43 ER_ROM0 __ROM0_BASE (__ROM0_SIZE - ER_CMSE_VENEER_SIZE) {
Dgcc_linker_script.ld33 ROM0 (rx) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE
/cmsis-dsp-latest/dsppp/linker_scripts/
Dac6_m0p_mps3_s.sct32 LR_ROM0 __ROM0_BASE __ROM0_SIZE {
35 ER_CMSE_VENEER __ROM0_BASE+__ROM0_SIZE -__ROM0_SIZE {
43 ER_ROM0 __ROM0_BASE (__ROM0_SIZE - ER_CMSE_VENEER_SIZE) {
Dac6_m4_mps3_s.sct32 LR_ROM0 __ROM0_BASE __ROM0_SIZE {
35 ER_CMSE_VENEER __ROM0_BASE+__ROM0_SIZE -__ROM0_SIZE {
43 ER_ROM0 __ROM0_BASE (__ROM0_SIZE - ER_CMSE_VENEER_SIZE) {
Dgcc_m0p_mps3.ld33 ROM0 (rx) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE
Dgcc_m4_mps3.ld33 ROM0 (rx) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE
/cmsis-dsp-latest/dsppp/RTE/Device/ARMCM0P/
Dac6_linker_script.sct32 LR_ROM0 __ROM0_BASE __ROM0_SIZE {
35 ER_CMSE_VENEER __ROM0_BASE+__ROM0_SIZE -__ROM0_SIZE {
43 ER_ROM0 __ROM0_BASE (__ROM0_SIZE - ER_CMSE_VENEER_SIZE) {
Dregions_ARMCM0P.h16 #define __ROM0_BASE 0x00000000 macro
Dgcc_linker_script.ld33 ROM0 (rx) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE
/cmsis-dsp-latest/Testing/cmsis_build/linker_scripts/
Dac6_m0p_mps3_s.sct32 LR_ROM0 __ROM0_BASE __ROM0_SIZE {
35 ER_CMSE_VENEER __ROM0_BASE+__ROM0_SIZE -__ROM0_SIZE {
43 ER_ROM0 __ROM0_BASE (__ROM0_SIZE - ER_CMSE_VENEER_SIZE) {
Dac6_m33_mps3_s.sct32 LR_ROM0 __ROM0_BASE __ROM0_SIZE {
35 ER_CMSE_VENEER __ROM0_BASE+__ROM0_SIZE -__ROM0_SIZE {
43 ER_ROM0 __ROM0_BASE (__ROM0_SIZE - ER_CMSE_VENEER_SIZE) {
Dac6_m3_mps3_s.sct32 LR_ROM0 __ROM0_BASE __ROM0_SIZE {
35 ER_CMSE_VENEER __ROM0_BASE+__ROM0_SIZE -__ROM0_SIZE {
43 ER_ROM0 __ROM0_BASE (__ROM0_SIZE - ER_CMSE_VENEER_SIZE) {
Dac6_m4_mps3_s.sct32 LR_ROM0 __ROM0_BASE __ROM0_SIZE {
35 ER_CMSE_VENEER __ROM0_BASE+__ROM0_SIZE -__ROM0_SIZE {
43 ER_ROM0 __ROM0_BASE (__ROM0_SIZE - ER_CMSE_VENEER_SIZE) {
Dac6_m7_mps3_s.sct32 LR_ROM0 __ROM0_BASE __ROM0_SIZE {
35 ER_CMSE_VENEER __ROM0_BASE+__ROM0_SIZE -__ROM0_SIZE {
43 ER_ROM0 __ROM0_BASE (__ROM0_SIZE - ER_CMSE_VENEER_SIZE) {
Dgcc_m0p_mps3.ld33 ROM0 (rx) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE
/cmsis-dsp-latest/Examples/cmsis_build/projects/RTE/Device/ARMCM0P/
Dregions_ARMCM0P.h16 #define __ROM0_BASE 0x00000000 macro
/cmsis-dsp-latest/Examples/cmsis_build/projects/RTE/Device/ARMCM7_DP/
Dregions_ARMCM7_DP.h16 #define __ROM0_BASE 0x00000000 macro
/cmsis-dsp-latest/dsppp/RTE/Device/ARMCM4/
Dregions_ARMCM4.h16 #define __ROM0_BASE 0x00000000 macro
/cmsis-dsp-latest/dsppp/linker_scripts/ARMCM0P/
Dregion_defs.h16 #define __ROM0_BASE 0x00000000 macro
/cmsis-dsp-latest/dsppp/linker_scripts/ARMCM4/
Dregion_defs.h16 #define __ROM0_BASE 0x00000000 macro
/cmsis-dsp-latest/Testing/cmsis_build/linker_scripts/ARMCM0P/
Dregion_defs.h16 #define __ROM0_BASE 0x00000000 macro
/cmsis-dsp-latest/Testing/cmsis_build/linker_scripts/ARMCM3/
Dregion_defs.h16 #define __ROM0_BASE 0x00000000 macro
/cmsis-dsp-latest/Testing/cmsis_build/linker_scripts/ARMCM33_DSP_FP/
Dregion_defs.h16 #define __ROM0_BASE 0x00000000 macro
/cmsis-dsp-latest/Testing/cmsis_build/linker_scripts/ARMCM4/
Dregion_defs.h16 #define __ROM0_BASE 0x00000000 macro
/cmsis-dsp-latest/Testing/cmsis_build/linker_scripts/ARMCM7_DP/
Dregion_defs.h16 #define __ROM0_BASE 0x00000000 macro

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