1/*
2 * Copyright (c) 2023 Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19/* ----------------------------------------------------------------------------
20  Stack seal size definition
21 *----------------------------------------------------------------------------*/
22#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
23#define __STACKSEAL_SIZE   ( 8 )
24#else
25#define __STACKSEAL_SIZE   ( 0 )
26#endif
27
28/* ----------------------------------------------------------------------------
29  Memory definition
30 *----------------------------------------------------------------------------*/
31MEMORY
32{
33  ROM0  (rx)  : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE
34#if __ROM1_SIZE > 0
35  ROM1  (rx)  : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE
36#endif
37#if __ROM2_SIZE > 0
38  ROM2  (rx)  : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE
39#endif
40#if __ROM3_SIZE > 0
41  ROM3  (rx)  : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE
42#endif
43
44  RAM0  (rwx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE
45#if __RAM1_SIZE > 0
46  RAM1  (rwx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE
47#endif
48#if __RAM2_SIZE > 0
49  RAM2  (rwx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE
50#endif
51#if __RAM3_SIZE > 0
52  RAM3  (rwx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE
53#endif
54}
55
56/* Linker script to place sections and symbol values. Should be used together
57 * with other linker script that defines memory regions FLASH and RAM.
58 * It references following symbols, which must be defined in code:
59 *   Reset_Handler : Entry of reset handler
60 *
61 * It defines following symbols, which code can use without definition:
62 *   __exidx_start
63 *   __exidx_end
64 *   __copy_table_start__
65 *   __copy_table_end__
66 *   __zero_table_start__
67 *   __zero_table_end__
68 *   __etext          (deprecated)
69 *   __data_start__
70 *   __preinit_array_start
71 *   __preinit_array_end
72 *   __init_array_start
73 *   __init_array_end
74 *   __fini_array_start
75 *   __fini_array_end
76 *   __data_end__
77 *   __bss_start__
78 *   __bss_end__
79 *   __end__
80 *   end
81 *   __HeapLimit
82 *   __StackLimit
83 *   __StackTop
84 *   __stack
85 */
86ENTRY(Reset_Handler)
87
88SECTIONS
89{
90  .text :
91  {
92    KEEP(*(.vectors))
93    *(.text*)
94
95    KEEP(*(.init))
96    KEEP(*(.fini))
97
98    /* .ctors */
99    *crtbegin.o(.ctors)
100    *crtbegin?.o(.ctors)
101    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
102    *(SORT(.ctors.*))
103    *(.ctors)
104
105    /* .dtors */
106    *crtbegin.o(.dtors)
107    *crtbegin?.o(.dtors)
108    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
109    *(SORT(.dtors.*))
110    *(.dtors)
111
112    *(.rodata*)
113
114    KEEP(*(.eh_frame*))
115  } > ROM0
116
117#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
118  .gnu.sgstubs :
119  {
120    . = ALIGN(32);
121  } > ROM0
122#endif
123
124  .ARM.extab :
125  {
126    *(.ARM.extab* .gnu.linkonce.armextab.*)
127  } > ROM0
128
129  __exidx_start = .;
130  .ARM.exidx :
131  {
132    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
133  } > ROM0
134  __exidx_end = .;
135
136  .copy.table :
137  {
138    . = ALIGN(4);
139    __copy_table_start__ = .;
140
141    LONG (LOADADDR(.data))
142    LONG (ADDR(.data))
143    LONG (SIZEOF(.data) / 4)
144
145    /* Add each additional data section here */
146/*
147    LONG (LOADADDR(.data2))
148    LONG (ADDR(.data2))
149    LONG (SIZEOF(.data2) / 4)
150*/
151    __copy_table_end__ = .;
152  } > ROM0
153
154  .zero.table :
155  {
156    . = ALIGN(4);
157    __zero_table_start__ = .;
158
159/*  .bss initialization to zero is already done during C Run-Time Startup.
160    LONG (ADDR(.bss))
161    LONG (SIZEOF(.bss) / 4)
162*/
163
164    /* Add each additional bss section here */
165/*
166    LONG (ADDR(.bss2))
167    LONG (SIZEOF(.bss2) / 4)
168*/
169    __zero_table_end__ = .;
170  } > ROM0
171
172  /*
173   * This __etext variable is kept for backward compatibility with older,
174   * ASM based startup files.
175   */
176  PROVIDE(__etext = LOADADDR(.data));
177
178  .data : ALIGN(4)
179  {
180    __data_start__ = .;
181    *(vtable)
182    *(.data)
183    *(.data.*)
184
185    . = ALIGN(4);
186    /* preinit data */
187    PROVIDE_HIDDEN (__preinit_array_start = .);
188    KEEP(*(.preinit_array))
189    PROVIDE_HIDDEN (__preinit_array_end = .);
190
191    . = ALIGN(4);
192    /* init data */
193    PROVIDE_HIDDEN (__init_array_start = .);
194    KEEP(*(SORT(.init_array.*)))
195    KEEP(*(.init_array))
196    PROVIDE_HIDDEN (__init_array_end = .);
197
198    . = ALIGN(4);
199    /* finit data */
200    PROVIDE_HIDDEN (__fini_array_start = .);
201    KEEP(*(SORT(.fini_array.*)))
202    KEEP(*(.fini_array))
203    PROVIDE_HIDDEN (__fini_array_end = .);
204
205    KEEP(*(.jcr*))
206    . = ALIGN(4);
207    /* All data end */
208    __data_end__ = .;
209
210  } > RAM0 AT > ROM0
211
212  /*
213   * Secondary data section, optional
214   *
215   * Remember to add each additional data section
216   * to the .copy.table above to assure proper
217   * initialization during startup.
218   */
219/*
220  .data2 : ALIGN(4)
221  {
222    . = ALIGN(4);
223    __data2_start__ = .;
224    *(.data2)
225    *(.data2.*)
226    . = ALIGN(4);
227    __data2_end__ = .;
228
229  } > RAM1 AT > ROM0
230*/
231
232  .bss :
233  {
234    . = ALIGN(4);
235    __bss_start__ = .;
236    *(.bss)
237    *(.bss.*)
238    *(COMMON)
239    . = ALIGN(4);
240    __bss_end__ = .;
241  } > RAM0 AT > RAM0
242
243  /*
244   * Secondary bss section, optional
245   *
246   * Remember to add each additional bss section
247   * to the .zero.table above to assure proper
248   * initialization during startup.
249   */
250/*
251  .bss2 :
252  {
253    . = ALIGN(4);
254    __bss2_start__ = .;
255    *(.bss2)
256    *(.bss2.*)
257    . = ALIGN(4);
258    __bss2_end__ = .;
259  } > RAM1 AT > RAM1
260*/
261
262  .heap (NOLOAD) :
263  {
264    . = ALIGN(8);
265    __end__ = .;
266    PROVIDE(end = .);
267    . = . + __HEAP_SIZE;
268    . = ALIGN(8);
269    __HeapLimit = .;
270  } > RAM0
271
272  .stack (ORIGIN(RAM0) + LENGTH(RAM0) - __STACK_SIZE - __STACKSEAL_SIZE) (NOLOAD) :
273  {
274    . = ALIGN(8);
275    __StackLimit = .;
276    . = . + __STACK_SIZE;
277    . = ALIGN(8);
278    __StackTop = .;
279  } > RAM0
280  PROVIDE(__stack = __StackTop);
281
282#if __STACKSEAL_SIZE > 0
283  .stackseal (ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE) (NOLOAD) :
284  {
285    . = ALIGN(8);
286    __StackSeal = .;
287    . = . + 8;
288    . = ALIGN(8);
289  } > RAM0
290#endif
291
292  /* Check if data + heap + stack exceeds RAM limit */
293  ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
294}
295