1/*
2 * Copyright (c) 2023 Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19/* ----------------------------------------------------------------------------
20  Stack seal size definition
21 *----------------------------------------------------------------------------*/
22#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
23#define __STACKSEAL_SIZE   ( 8 )
24#else
25#define __STACKSEAL_SIZE   ( 0 )
26#endif
27
28/*----------------------------------------------------------------------------
29  Scatter File Definitions definition
30 *----------------------------------------------------------------------------*/
31
32LR_ROM0 __ROM0_BASE __ROM0_SIZE  {
33
34#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
35  ER_CMSE_VENEER __ROM0_BASE+__ROM0_SIZE -__ROM0_SIZE {
36   *(Veneer$$CMSE)
37  }
38  #define ER_CMSE_VENEER_SIZE AlignExpr(ImageLength(ER_CMSE_VENEER), 8)
39#else
40  #define ER_CMSE_VENEER_SIZE 0
41#endif
42
43  ER_ROM0 __ROM0_BASE (__ROM0_SIZE - ER_CMSE_VENEER_SIZE) {
44   *.o (RESET, +First)
45   *(InRoot$$Sections)
46   *(+RO +XO)
47  }
48
49  RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE) {
50    *(.bss.noinit)
51  }
52
53  RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
54    *(+RW +ZI)
55  }
56
57#if __HEAP_SIZE > 0
58  ARM_LIB_HEAP  (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE  {   ; Reserve empty region for heap
59  }
60#endif
61
62  ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE {   ; Reserve empty region for stack
63  }
64
65#if __STACKSEAL_SIZE > 0
66  STACKSEAL +0 EMPTY 8 {             ; Reserve empty region for stack seal immediately after stack
67  }
68#endif
69
70#if __RAM1_SIZE > 0
71  RW_RAM1 __RAM1_BASE __RAM1_SIZE  {
72   .ANY (+RW +ZI)
73  }
74#endif
75
76#if __RAM2_SIZE > 0
77  RW_RAM2 __RAM2_BASE __RAM2_SIZE  {
78   .ANY (+RW +ZI)
79  }
80#endif
81
82#if __RAM3_SIZE > 0
83  RW_RAM3 __RAM3_BASE __RAM3_SIZE  {
84   .ANY (+RW +ZI)
85  }
86#endif
87}
88
89#if __ROM1_SIZE > 0
90LR_ROM1 __ROM1_BASE __ROM1_SIZE  {
91  ER_ROM1 +0 __ROM1_SIZE {
92   .ANY (+RO +XO)
93  }
94}
95#endif
96
97#if __ROM2_SIZE > 0
98LR_ROM2 __ROM2_BASE __ROM2_SIZE  {
99  ER_ROM2 +0 __ROM2_SIZE {
100   .ANY (+RO +XO)
101  }
102}
103#endif
104
105#if __ROM3_SIZE > 0
106LR_ROM3 __ROM3_BASE __ROM3_SIZE  {
107  ER_ROM3 +0 __ROM3_SIZE {
108   .ANY (+RO +XO)
109  }
110}
111#endif
112