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/cmsis-dsp-latest/dsppp/RTE/Device/SSE_300_MPS3/
Dac6_linker_script.sct49 RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE) {
53 …RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - AlignExpr(ImageLength(RW_NOIN…
62 …ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve emp…
Dregions_V2M_MPS3_SSE_300_FVP.h24 #define __RAM0_SIZE 0x00200000 macro
/cmsis-dsp-latest/dsppp/linker_scripts/
Dac6_m0p_mps3_s.sct49 RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE) {
53 …RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - AlignExpr(ImageLength(RW_NOIN…
62 …ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve emp…
Dac6_m4_mps3_s.sct49 RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE) {
53 …RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - AlignExpr(ImageLength(RW_NOIN…
62 …ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve emp…
Dgcc_m0p_mps3.ld44 RAM0 (rwx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE
/cmsis-dsp-latest/dsppp/RTE/Device/ARMCM0P/
Dac6_linker_script.sct49 RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE) {
53 …RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - AlignExpr(ImageLength(RW_NOIN…
62 …ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve emp…
Dregions_ARMCM0P.h41 #define __RAM0_SIZE 0x00020000 macro
/cmsis-dsp-latest/Testing/cmsis_build/linker_scripts/
Dac6_m0p_mps3_s.sct49 RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE) {
53 …RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - AlignExpr(ImageLength(RW_NOIN…
62 …ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve emp…
Dac6_m33_mps3_s.sct49 RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE) {
53 …RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - AlignExpr(ImageLength(RW_NOIN…
62 …ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve emp…
Dac6_m3_mps3_s.sct49 RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE) {
53 …RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - AlignExpr(ImageLength(RW_NOIN…
62 …ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve emp…
Dac6_m4_mps3_s.sct49 RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE) {
53 …RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - AlignExpr(ImageLength(RW_NOIN…
62 …ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve emp…
Dac6_m7_mps3_s.sct49 RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE) {
53 …RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - AlignExpr(ImageLength(RW_NOIN…
62 …ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve emp…
/cmsis-dsp-latest/Examples/cmsis_build/projects/RTE/Device/ARMCM0P/
Dregions_ARMCM0P.h41 #define __RAM0_SIZE 0x00020000 macro
/cmsis-dsp-latest/Examples/cmsis_build/projects/RTE/Device/ARMCM7_DP/
Dregions_ARMCM7_DP.h41 #define __RAM0_SIZE 0x00020000 macro
/cmsis-dsp-latest/dsppp/RTE/Device/ARMCM4/
Dregions_ARMCM4.h41 #define __RAM0_SIZE 0x00020000 macro
/cmsis-dsp-latest/dsppp/linker_scripts/ARMCM0P/
Dregion_defs.h41 #define __RAM0_SIZE 0x00040000 macro
/cmsis-dsp-latest/dsppp/linker_scripts/ARMCM4/
Dregion_defs.h41 #define __RAM0_SIZE 0x00040000 macro
/cmsis-dsp-latest/Testing/cmsis_build/linker_scripts/ARMCM0P/
Dregion_defs.h41 #define __RAM0_SIZE 0x00200000 macro
/cmsis-dsp-latest/Testing/cmsis_build/linker_scripts/ARMCM3/
Dregion_defs.h41 #define __RAM0_SIZE 0x00200000 macro
/cmsis-dsp-latest/Testing/cmsis_build/linker_scripts/ARMCM33_DSP_FP/
Dregion_defs.h41 #define __RAM0_SIZE 0x00200000 macro
/cmsis-dsp-latest/Testing/cmsis_build/linker_scripts/ARMCM4/
Dregion_defs.h41 #define __RAM0_SIZE 0x00200000 macro
/cmsis-dsp-latest/Testing/cmsis_build/linker_scripts/ARMCM7_DP/
Dregion_defs.h41 #define __RAM0_SIZE 0x00200000 macro
/cmsis-dsp-latest/Examples/cmsis_build/projects/RTE/Device/SSE_300_MPS3/
Dregions_SSE_300_MPS3.h24 #define __RAM0_SIZE 0x00080000 macro
/cmsis-dsp-latest/Examples/cmsis_build/projects/RTE/Device/SSE_310_MPS3/
Dregions_SSE_310_MPS3.h24 #define __RAM0_SIZE 0x00008000 macro
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/SSE-310-MPS3/
Dregions_SSE-310-MPS3.h24 #define __RAM0_SIZE 0x00008000 macro

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