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Searched refs:write_reg_mask (Results 1 – 12 of 12) sorted by relevance

/Zephyr-latest/drivers/sensor/adi/adxl367/
Dadxl367.c43 ret = data->hw_tf->write_reg_mask(dev, ADXL367_ACT_INACT_CTL, in adxl367_setup_activity_detection()
53 ret = data->hw_tf->write_reg_mask(dev, ADXL367_THRESH_ACT_H, ADXL367_THRESH_H_MSK, in adxl367_setup_activity_detection()
59 return data->hw_tf->write_reg_mask(dev, ADXL367_THRESH_ACT_L, ADXL367_THRESH_L_MSK, in adxl367_setup_activity_detection()
80 ret = data->hw_tf->write_reg_mask(dev, ADXL367_ACT_INACT_CTL, in adxl367_setup_inactivity_detection()
91 ret = data->hw_tf->write_reg_mask(dev, ADXL367_THRESH_INACT_H, ADXL367_THRESH_H_MSK, in adxl367_setup_inactivity_detection()
97 return data->hw_tf->write_reg_mask(dev, ADXL367_THRESH_INACT_L, ADXL367_THRESH_L_MSK, in adxl367_setup_inactivity_detection()
122 ret = data->hw_tf->write_reg_mask(dev, ADXL367_POWER_CTL, in adxl367_set_op_mode()
157 ret = data->hw_tf->write_reg_mask(dev, ADXL367_POWER_CTL, in adxl367_set_autosleep()
185 ret = data->hw_tf->write_reg_mask(dev, ADXL367_POWER_CTL, in adxl367_set_low_noise()
215 return data->hw_tf->write_reg_mask(dev, ADXL367_ACT_INACT_CTL, in adxl367_set_act_proc_mode()
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Dadxl367_i2c.c86 .write_reg_mask = adxl367_i2c_reg_write_mask,
Dadxl367_spi.c111 .write_reg_mask = adxl367_spi_reg_write_mask,
Dadxl367_trigger.c125 ret = drv_data->hw_tf->write_reg_mask(dev, ADXL367_INTMAP1_LOWER, int_mask, int_en); in adxl367_trigger_set()
Dadxl367.h332 int (*write_reg_mask)(const struct device *dev, uint8_t reg_addr, member
Dadxl367_stream.c118 rc = data->hw_tf->write_reg_mask(dev, ADXL367_INTMAP1_LOWER, int_mask, int_value); in adxl367_submit_stream()
/Zephyr-latest/drivers/sensor/adi/adxl372/
Dadxl372.c94 int ret = data->hw_tf->write_reg_mask(dev, ADXL372_POWER_CTL, in adxl372_set_op_mode()
120 return data->hw_tf->write_reg_mask(dev, ADXL372_MEASURE, in adxl372_set_autosleep()
150 ret = data->hw_tf->write_reg_mask(dev, ADXL372_POWER_CTL, in adxl372_set_bandwidth()
161 return data->hw_tf->write_reg_mask(dev, ADXL372_MEASURE, in adxl372_set_bandwidth()
191 ret = data->hw_tf->write_reg_mask(dev, ADXL372_POWER_CTL, in adxl372_set_hpf_corner()
220 return data->hw_tf->write_reg_mask(dev, ADXL372_MEASURE, in adxl372_set_act_proc_mode()
240 return data->hw_tf->write_reg_mask(dev, ADXL372_TIMING, in adxl372_set_odr()
258 int ret = data->hw_tf->write_reg_mask(dev, ADXL372_POWER_CTL, in adxl372_set_instant_on_th()
291 return data->hw_tf->write_reg_mask(dev, ADXL372_TIMING, in adxl372_set_wakeup_rate()
343 int ret = data->hw_tf->write_reg_mask(dev, ADXL372_POWER_CTL, in adxl372_set_filter_settle()
Dadxl372_i2c.c88 .write_reg_mask = adxl372_i2c_reg_write_mask,
Dadxl372_spi.c102 .write_reg_mask = adxl372_spi_reg_write_mask,
Dadxl372_trigger.c140 ret = drv_data->hw_tf->write_reg_mask(dev, ADXL372_INT1_MAP, int_mask, int_en); in adxl372_trigger_set()
Dadxl372.h306 int (*write_reg_mask)(const struct device *dev, uint8_t reg_addr, member
Dadxl372_stream.c96 rc = data->hw_tf->write_reg_mask(dev, ADXL372_INT1_MAP, in adxl372_submit_stream()