43 	ret = data->hw_tf->write_reg_mask(dev, ADXL367_ACT_INACT_CTL,  in adxl367_setup_activity_detection()
53 	ret = data->hw_tf->write_reg_mask(dev, ADXL367_THRESH_ACT_H, ADXL367_THRESH_H_MSK,  in adxl367_setup_activity_detection()
59 	return data->hw_tf->write_reg_mask(dev, ADXL367_THRESH_ACT_L, ADXL367_THRESH_L_MSK,  in adxl367_setup_activity_detection()
80 	ret = data->hw_tf->write_reg_mask(dev, ADXL367_ACT_INACT_CTL,  in adxl367_setup_inactivity_detection()
91 	ret = data->hw_tf->write_reg_mask(dev, ADXL367_THRESH_INACT_H, ADXL367_THRESH_H_MSK,  in adxl367_setup_inactivity_detection()
97 	return data->hw_tf->write_reg_mask(dev, ADXL367_THRESH_INACT_L, ADXL367_THRESH_L_MSK,  in adxl367_setup_inactivity_detection()
122 	ret = data->hw_tf->write_reg_mask(dev, ADXL367_POWER_CTL,  in adxl367_set_op_mode()
157 	ret = data->hw_tf->write_reg_mask(dev, ADXL367_POWER_CTL,  in adxl367_set_autosleep()
185 	ret = data->hw_tf->write_reg_mask(dev, ADXL367_POWER_CTL,  in adxl367_set_low_noise()
215 	return data->hw_tf->write_reg_mask(dev, ADXL367_ACT_INACT_CTL,  in adxl367_set_act_proc_mode()
238 	ret = data->hw_tf->write_reg_mask(dev,  in adxl367_set_output_rate()
268 	ret = data->hw_tf->write_reg_mask(dev,  in adxl367_set_range()
364 	ret = data->hw_tf->write_reg_mask(dev, ADXL367_SELF_TEST, ADXL367_SELF_TEST_ST_MSK,  in adxl367_self_test()
385 	ret = data->hw_tf->write_reg_mask(dev, ADXL367_SELF_TEST,  in adxl367_self_test()
412 	ret = data->hw_tf->write_reg_mask(dev, ADXL367_SELF_TEST, ADXL367_SELF_TEST_ST_FORCE_MSK |  in adxl367_self_test()
448 	return data->hw_tf->write_reg_mask(dev,  in adxl367_temp_read_en()
471 	ret = data->hw_tf->write_reg_mask(dev, ADXL367_FIFO_CONTROL,  in adxl367_set_fifo_sample_sets_nb()
500 	return data->hw_tf->write_reg_mask(dev,  in adxl367_set_fifo_mode()
523 	return data->hw_tf->write_reg_mask(dev, ADXL367_ADC_CTL,  in adxl367_set_fifo_read_mode()
554 	ret = data->hw_tf->write_reg_mask(dev,  in adxl367_set_fifo_format()