Home
last modified time | relevance | path

Searched refs:u (Results 1 – 25 of 296) sorted by relevance

12345678910>>...12

/Zephyr-latest/subsys/net/lib/http/
Dhttp_parser_url.c382 int http_parse_host(const char *buf, struct http_parser_url *u, in http_parse_host() argument
389 buflen = u->field_data[UF_HOST].off + u->field_data[UF_HOST].len; in http_parse_host()
390 __ASSERT_NO_MSG(u->field_set & (1 << UF_HOST)); in http_parse_host()
392 u->field_data[UF_HOST].len = 0U; in http_parse_host()
396 for (p = buf + u->field_data[UF_HOST].off; p < buf + buflen; p++) { in http_parse_host()
406 u->field_data[UF_HOST].off = p - buf; in http_parse_host()
408 u->field_data[UF_HOST].len++; in http_parse_host()
413 u->field_data[UF_HOST].off = p - buf; in http_parse_host()
415 u->field_data[UF_HOST].len++; in http_parse_host()
420 u->field_data[UF_HOST].len++; in http_parse_host()
[all …]
/Zephyr-latest/tests/bluetooth/uuid/src/
Dtest_bt_uuid_create.c23 } u; in ZTEST() local
26 zassert_true(bt_uuid_create(&u.uuid, le16, sizeof(le16)), in ZTEST()
30 zassert_true(bt_uuid_cmp(&u.uuid, BT_UUID_DECLARE_16(0x0001)) == 0, in ZTEST()
34 zassert_true(bt_uuid_cmp(&u.uuid, &le_128.uuid) == 0, in ZTEST()
38 zassert_false(bt_uuid_cmp(&u.uuid, BT_UUID_DECLARE_16(0x0100)) == 0, in ZTEST()
42 zassert_true(bt_uuid_create(&u.uuid, be16, sizeof(be16)), in ZTEST()
46 zassert_false(bt_uuid_cmp(&u.uuid, BT_UUID_DECLARE_16(0x0001)) == 0, in ZTEST()
50 zassert_false(bt_uuid_cmp(&u.uuid, &le_128.uuid) == 0, in ZTEST()
54 zassert_true(bt_uuid_cmp(&u.uuid, BT_UUID_DECLARE_16(0x0100)) == 0, in ZTEST()
/Zephyr-latest/drivers/xen/dom0/
Ddomctl.c28 .u.scheduler_op = *sched_op, in xen_domctl_scheduler_op()
69 .u.vcpucontext.vcpu = 0, in xen_domctl_getvcpucontext()
72 set_xen_guest_handle(domctl.u.vcpucontext.ctxt, ctxt); in xen_domctl_getvcpucontext()
82 .u.vcpucontext.vcpu = 0, in xen_domctl_setvcpucontext()
85 set_xen_guest_handle(domctl.u.vcpucontext.ctxt, ctxt); in xen_domctl_setvcpucontext()
103 memcpy(dom_info, &domctl.u.getdomaininfo, sizeof(*dom_info)); in xen_domctl_getdomaininfo()
121 *size_mb = domctl.u.paging_mempool.size; in xen_domctl_get_paging_mempool_size()
131 .u.paging_mempool.size = size_mb, in xen_domctl_set_paging_mempool_size()
142 .u.max_mem.max_memkb = max_memkb, in xen_domctl_max_mem()
153 .u.address_size.size = addr_size, in xen_domctl_set_address_size()
[all …]
/Zephyr-latest/subsys/tracing/sysview/
DSYSVIEW_Zephyr.txt9 NamedType TimeOut *="%u ticks" 0=TIMEOUT_NO_WAIT 4294967295=FOREVER
32 34 k_busy_wait Timeout=%u us
34 35 irq_enable irq=%u
35 36 irq_disable irq=%u
41 40 k_sem_init sem=%I, initial_count=%u, | Returns %ErrCodePosix
59 55 k_stack_init stack=%I, buffer=%p, num_entries=%u
64 59 k_msgq_init msgq=%I, buffer=%p, msg_size=%u, max_msgs=%us
78 71 k_pipe_init pipe=%I, buffer=%p, size=%u
80 73 k_pipe_put pipe=%I, data=%p, bytes_to_write=%u, bytes_written=%u, min_xfer=%u, …
81 74 k_pipe_get pipe=%I, data=%p, bytes_to_read=%u, bytes_read=%u, min_xfer=%u, Time…
[all …]
/Zephyr-latest/tests/lib/c_lib/common/src/
Dtest_sqrt.c44 union { uint64_t u; double d; } ieee754; in isinf() member
46 ieee754.u &= ~0x8000000000000000; /* ignore the sign */ in isinf()
47 return ((ieee754.u >> 52) == 0x7FF) && in isinf()
48 ((ieee754.u & 0x000fffffffffffff) == 0); in isinf()
55 union { uint64_t u; double d; } ieee754; in isnan() member
57 ieee754.u &= ~0x8000000000000000; /* ignore the sign */ in isnan()
58 return ((ieee754.u >> 52) == 0x7FF) && in isnan()
59 ((ieee754.u & 0x000fffffffffffff) != 0); in isnan()
66 union { uint32_t u; float f; } ieee754; in isinff() member
68 ieee754.u &= ~0x80000000; /* ignore the sign */ in isinff()
[all …]
/Zephyr-latest/samples/posix/eventfd/src/
Dmain.c28 uint64_t u; in writer() local
33 u = strtoull(g_argv[j], NULL, 0); in writer()
34 s = write(efd, &u, sizeof(uint64_t)); in writer()
44 uint64_t u; in reader() local
50 s = read(efd, &u, sizeof(uint64_t)); in reader()
55 (unsigned long long)u, (unsigned long long)u); in reader()
/Zephyr-latest/tests/net/lib/http_header_fields/src/
Dmain.c47 struct http_parser_url u; member
56 .u = { .field_set = (1 << UF_SCHEMA) | (1 << UF_HOST) | (1 << UF_PATH),
73 .u = { .field_set = (1 << UF_SCHEMA) | (1 << UF_HOST) |
91 .u = { .field_set = (1 << UF_HOST) | (1 << UF_PORT),
115 .u = { .field_set = (1 << UF_SCHEMA) | (1 << UF_HOST) | (1 << UF_PATH),
132 .u = { .field_set = (1 << UF_SCHEMA) | (1 << UF_HOST) |
150 .u = { .field_set = (1 << UF_HOST) | (1 << UF_PORT),
167 .u = { .field_set = (1 << UF_SCHEMA) | (1 << UF_HOST) | (1 << UF_PATH),
187 .u = { .field_set = (1<<UF_SCHEMA) | (1<<UF_HOST) | (1<<UF_PATH) |
205 .u = { .field_set = (1<<UF_PATH) | (1<<UF_QUERY),
[all …]
/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_qspi.h25 #define MCHP_QMSPI_SPI_MODE0 0u
45 #define MCHP_QMSPI_M_ACT_SRST_OFS 0u
141 #define MCHP_QMSPI_M_CPHA_MOSI_CE1 0u
147 #define MCHP_QMSPI_M_CPHA_MISO_CE1 0u
154 #define MCHP_QMSPI_M_SIG_MODE0_VAL 0u
158 #define MCHP_QMSPI_M_SIG_MODE0 0u
165 #define MCHP_QMSPI_M_CS0 SHLU32(0u, 12)
176 #define MCHP_QMSPI_C_IFM_1X 0u
181 #define MCHP_QMSPI_C_TX_DIS 0u
187 #define MCHP_QMSPI_C_TX_DMA_DIS 0u
[all …]
Dmec172x_espi_iom.h31 #define MCHP_ESPI_GBL_CAP1_MAX_FREQ_POS 0u
41 #define MCHP_ESPI_GBL_CAP1_ALERT_ON_IO1 0u
45 #define MCHP_ESPI_GBL_CAP1_IO_MODE0_1 0u
105 #define MCHP_ESPI_FC_CAP_SHARE_MAF_ONLY 0u
138 #define MCHP_ESPI_RST_ISTS_POS 0u
149 #define MCHP_ESPI_PLTRST_SRC_POS 0u
178 #define MCHP_ESPI_VW_ERR_STS_FATAL_POS 0u
203 #define MCHP_ESPI_PC_LC_LEN_POS 0u
247 #define MCHP_ESPI_LTR_STS_TX_DONE_POS 0u /* RW1C */
256 #define MCHP_ESPI_LTR_IEN_TX_DONE_POS 0u
[all …]
Dmec172x_espi_vw.h15 #define ESPI_M2SW0_OFS 0u
21 #define ESPI_M2SW0_MTOS_SRC_ESPI_RST 0u
88 #define ESPI_S2MW0_STOM_SRC_ESPI_RST 0u
113 #define ESPI_S2MW1_SRC0_POS 0u
144 #define MSVW_INDEX_OFS 0u
156 #define SMVW_INDEX_OFS 0u
166 #define MEC_MSVW_SRC0_IRQ_SEL_POS 0u
195 #define MEC_MSVW_SRC0_POS 0u
224 MSVW_SRC0 = 0u,
231 SMVW_SRC0 = 0u,
[all …]
/Zephyr-latest/drivers/stepper/
Dgpio_stepper_controller.c23 {1u, 1u, 0u, 0u}, {0u, 1u, 0u, 0u}, {0u, 1u, 1u, 0u}, {0u, 0u, 1u, 0u},
24 {0u, 0u, 1u, 1u}, {0u, 0u, 0u, 1u}, {1u, 0u, 0u, 1u}, {1u, 0u, 0u, 0u}};
86 const int err = gpio_pin_set_dt(&config->control_pins[i], 0u); in power_down_coils()
/Zephyr-latest/soc/infineon/cat1a/psoc6_legacy/
Dsoc.c63 Cy_SysClk_ClkFastSetDivider(0u); in Cy_SysClk_ClkFastInit()
72 Cy_SysClk_ClkHfSetSource(0u, CY_SYSCLK_CLKHF_IN_CLKPATH0); in Cy_SysClk_ClkHf0Init()
73 Cy_SysClk_ClkHfSetDivider(0u, CY_SYSCLK_CLKHF_NO_DIVIDE); in Cy_SysClk_ClkHf0Init()
74 Cy_SysClk_ClkHfEnable(0u); in Cy_SysClk_ClkHf0Init()
88 Cy_SysClk_ClkPathSetSource(0u, CY_SYSCLK_CLKPATH_IN_IMO); in Cy_SysClk_ClkPath0Init()
112 Cy_SysClk_ClkSlowSetDivider(0u); in Cy_SysClk_ClkSlowInit()
377 Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0u, 0u); in Cy_SystemInit()
378 Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0u); in Cy_SystemInit()
/Zephyr-latest/soc/microchip/mec/common/reg/
Dmec_adc.h24 #define MCHP_ADC_CTRL_REG_OFS 0u
39 #define MCHP_ADC_DELAY_START_POS 0u
107 #define MCHP_ADC_CH_VREF_SEL_PAD(n) 0u
111 #define MCHP_ADC_CH_VREF_SEL_PAD(n) 0u
125 #define MCHP_ADC_VREF_CTRL_PAD_UNUSED_FLOAT 0u
136 #define MCHP_ADC_SAR_CTRL_SELDIFF_DIS 0u
146 #define MCHP_ADC_SAR_CTRL_SHIFTD_DIS 0u
Dmec_ps2.h24 #define MCHP_PS2_CTRL_TR_POS 0u
25 #define MCHP_PS2_CTRL_TR_RX 0u
36 #define MCHP_PS2_CTRL_PAR_ODD 0u
45 #define MCHP_PS2_CTRL_STOP_ACT_HI 0u
Dmec_wdt.h20 #define MCHP_WDT_CTRL_EN_POS 0u
44 #define MCHP_WDT_CTRL_MODE_RESET 0u
59 #define MCHP_WDT_STS_EVENT_IRQ_POS 0u
65 #define MCHP_WDT_IEN_EVENT_IRQ_POS 0u
Dmec_pwm.h17 #define MCHP_PWM_COUNT_ON_REG_OFS 0u
35 #define MCHP_PWM_CFG_CLK_SEL_48M 0u
42 #define MCHP_PWM_CFG_ON_POL_HI 0u
Dmec_uart.h26 #define MCHP_UART_RTXB_OFS 0u
27 #define MCHP_UART_BRGD_LSB_OFS 0u
137 #define MCHP_UART_LD_CFG_INTCLK 0u
138 #define MCHP_UART_LD_CFG_NO_INVERT 0u
139 #define MCHP_UART_LD_CFG_RESET_SYS 0u
/Zephyr-latest/boards/u-blox/
Dindex.rst1 .. _boards-u-blox:
3 u-blox
/Zephyr-latest/drivers/gpio/
Dgpio_mchp_mec5.c82 uint32_t pin_num = 0u; in gpio_mec5_configure()
83 uint32_t port_num = 0u; in gpio_mec5_configure()
84 uint32_t temp = 0u; in gpio_mec5_configure()
132 props[idx].val = 0u; in gpio_mec5_configure()
136 props[idx].val = 0u; in gpio_mec5_configure()
213 uint8_t en = 0u; in gpio_mec5_intr_en()
314 int ret = mec_hal_gpio_parout_port_mask(port_num, 0u, (const uint32_t)mask); in gpio_mec5_port_clear_bits_raw()
366 uint32_t valid_msk = 0u; in gpio_mec5_get_direction()
367 uint32_t pin_num = 0u, port_num = 0u; in gpio_mec5_get_direction()
369 uint8_t pwr_gate = 0u, dir = 0u, in_pad_dis = 0u; in gpio_mec5_get_direction()
[all …]
/Zephyr-latest/drivers/modem/
DKconfig.ublox-sara-r41 # u-blox SARA R4 driver options
15 Choose this setting to enable u-blox SARA-R4 LTE-CatM1/NB-IoT modem
21 bool "u-blox SARA variant selection"
25 bool "u-blox SARA-R4"
30 bool "u-blox SARA-U2"
42 int "Stack size for the u-blox SARA-R4 modem driver RX thread"
45 This stack is used by the u-blox SARA-R4 RX thread.
48 int "Stack size for the u-blox SARA-R4 modem driver work queue"
85 int "u-blox SARA-R4 driver init priority"
88 u-blox SARA-R4 device driver initialization priority.
[all …]
/Zephyr-latest/drivers/tee/optee/
Doptee.c127 memset(&mtp->u, 0, sizeof(mtp->u)); in param_to_msg_param()
134 mtp->u.value.a = tp->a; in param_to_msg_param()
135 mtp->u.value.b = tp->b; in param_to_msg_param()
136 mtp->u.value.c = tp->c; in param_to_msg_param()
143 mtp->u.rmem.shm_ref = tp->c; in param_to_msg_param()
144 mtp->u.rmem.size = tp->b; in param_to_msg_param()
145 mtp->u.rmem.offs = tp->a; in param_to_msg_param()
158 struct tee_shm *shm = (struct tee_shm *)mp->u.tmem.shm_ref; in msg_param_to_tmp_mem()
161 p->b = mp->u.tmem.size; in msg_param_to_tmp_mem()
169 p->a = mp->u.tmem.buf_ptr - k_mem_phys_addr(shm->addr); in msg_param_to_tmp_mem()
[all …]
/Zephyr-latest/boards/u-blox/ubx_evkannab1/
DKconfig.defconfig1 # u-blox EVK-ANNA-B1 board configuration
3 # Copyright (c) 2021 u-blox AG
DKconfig.ubx_evkannab11 # u-blox EVK-ANNA-B1 board configuration
3 # Copyright (c) 2021 u-blox AG
/Zephyr-latest/boards/u-blox/ubx_evkninab1/
DKconfig.defconfig1 # u-blox EVK-NINA-B1 board configuration
3 # Copyright (c) 2021 u-blox AG
DKconfig.ubx_evkninab11 # u-blox EVK-NINA-B1 board configuration
3 # Copyright (c) 2021 u-blox AG

12345678910>>...12