/Zephyr-latest/soc/ite/ec/common/ |
D | vector.S | 32 lb t1, 0(t0) 33 ori t1, t1, IT8XXX2_GCTRL_JTAG 34 sb t1, 0(t0) 37 li t1, 0 39 sb t1, 0(t0) 41 sb t1, 1(t0) 43 sb t1, 4(t0) 45 sb t1, 5(t0) 47 sb t1, 6(t0) 51 sb t1, 0(t0) [all …]
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/Zephyr-latest/arch/riscv/core/ |
D | isr.S | 28 RV_E( op t1, __struct_arch_esf_t1_OFFSET(sp) );\ 145 sr t1, _curr_cpu_arch_user_exc_tmp1(s0) 149 li t1, MSTATUS_MPP 150 and t0, t0, t1 183 lr t1, _curr_cpu_arch_user_exc_tmp1(s0) 211 li t1, MSTATUS_FS 212 and t1, t1, t2 213 bnez t1, no_fp 216 li t1, CONFIG_RISCV_MCAUSE_EXCEPTION_MASK 217 and t2, t2, t1 [all …]
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D | reset.S | 66 li t1, __z_interrupt_all_stacks_SIZEOF 67 add t1, t1, t0 74 blt t0, t1, aa_loop 98 li t1, -1 99 sr t1, 0(t0) 113 li t1, 1 114 sr t1, 0(t0)
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D | pmp.S | 40 slli t1, a0, 4 /* 16-byte instruction blocks */ 41 add t0, t0, t1 51 li t1, _index + 1 53 beq t1, a1, pmpaddr_done 67 slli t1, a0, 4 /* 16-byte instruction blocks */ 68 add t0, t0, t1
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D | coredump.c | 23 uint64_t t1; member 44 uint32_t t1; 93 arch_blk.r.t1 = esf->t1; in arch_coredump_info_dump()
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/Zephyr-latest/soc/openisa/rv32m1/ |
D | soc_irq.S | 34 li t1, 1 35 sll t1, t1, a0 36 sw t1, 0x00(t0) 53 csrr t1, RI5CY_LPEND0 56 sw t1, __soc_esf_t_lpend0_OFFSET(a0) 59 csrr t1, RI5CY_LPEND1 62 sw t1, __soc_esf_t_lpend1_OFFSET(a0) 71 lw t1, __soc_esf_t_lpend0_OFFSET(a0) 74 csrw RI5CY_LPEND0, t1 77 lw t1, __soc_esf_t_lpend1_OFFSET(a0) [all …]
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D | wdog.S | 45 li t1, WDOG_BASE 49 sw t2, WDOG_CNT_OFFSET(t1) 52 lw t2, WDOG_CS_OFFSET(t1) 55 sw t2, WDOG_CS_OFFSET(t1) 59 sw t2, WDOG_TOVAL_OFFSET(t1)
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/Zephyr-latest/arch/mips/core/ |
D | isr.S | 44 op t1, ESF_O(t1)(sp) ;\ 91 mflo t1 93 OP_STOREREG t1, ESF_O(lo)(sp) 96 mfc0 t1, CP0_BADVADDR 97 OP_STOREREG t1, ESF_O(badvaddr)(sp) 100 mfc0 t1, CP0_CAUSE 101 OP_STOREREG t1, ESF_O(cause)(sp) 107 and k1, k0, t1 115 and t1, t1, t0 117 and a0, a0, t1 [all …]
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D | reset.S | 35 li t1, CONFIG_ISR_STACK_SIZE 36 add t1, t1, t0 43 blt t0, t1, aa_loop
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/Zephyr-latest/tests/net/trickle/src/ |
D | main.c | 62 static struct net_trickle t1; variable 89 ret = net_trickle_create(&t1, T1_IMIN, T1_IMAX, T1_K); in test_trickle_create() 103 ret = net_trickle_start(&t1, cb_1, &t1); in test_trickle_start() 112 zassert_false(net_trickle_stop(&t1), in test_trickle_stop() 121 zassert_true(net_trickle_is_running(&t1), "Trickle 1 not running"); in test_trickle_1_status() 124 net_trickle_inconsistency(&t1); in test_trickle_1_status() 126 net_trickle_consistency(&t1); in test_trickle_1_status() 147 zassert_true(net_trickle_is_running(&t1), "Trickle 1 not running"); in test_trickle_1_wait() 159 zassert_true(net_trickle_is_running(&t1), "Trickle 1 not running"); in test_trickle_1_wait_long() 179 zassert_false(net_trickle_is_running(&t1), "Trickle 1 running"); in test_trickle_1_stopped() [all …]
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/Zephyr-latest/soc/telink/tlsr/tlsr951x/ |
D | start.S | 56 la t1, _RETENTION_DATA_LMA_START 61 lw t0, 0(t1) 63 addi t1, t1, 4 68 la t1, _RAMCODE_LMA_START 73 lw t0, 0(t1) 75 addi t1, t1, 4
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D | soc_irq.S | 28 csrr t1, ucode 35 sw t1, __soc_esf_t_ucode_OFFSET(a0) 45 lw t1, __soc_esf_t_ucode_OFFSET(a0) 52 csrw ucode, t1
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/Zephyr-latest/soc/neorv32/ |
D | soc_irq.S | 21 li t1, 1 22 sll t0, t1, a0 24 and t1, t2, t0 25 csrrs t2, mie, t1
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/Zephyr-latest/soc/nordic/common/vpr/ |
D | soc_isr_stacking.h | 29 unsigned long t1; \ 51 unsigned long t1; \ 93 addi t1, sp, __struct_arch_esf_soc_context_OFFSET; \ 96 sr t0, __soc_esf_t_sp_align_OFFSET(t1) 99 addi t1, sp, __struct_arch_esf_soc_context_OFFSET; \ 100 lr t0, __soc_esf_t_sp_align_OFFSET(t1); \ 101 lr t1, __struct_arch_esf_mepc_OFFSET(sp); \ 102 or t2, t1, t0; \
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/Zephyr-latest/tests/kernel/tickless/tickless_concept/src/ |
D | main.c | 71 volatile uint32_t t0, t1; in ZTEST() local 76 t1 = k_uptime_get_32(); in ZTEST() 77 TC_PRINT("time %d, %d\n", t0, t1); in ZTEST() 79 zassert_true((t1 - t0) >= SLEEP_TICKLESS); in ZTEST() 84 t1 = k_uptime_get_32(); in ZTEST() 85 TC_PRINT("time %d, %d\n", t0, t1); in ZTEST() 87 zassert_true((t1 - t0) >= SLEEP_TICKFUL); in ZTEST()
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/Zephyr-latest/soc/andestech/ae350/ |
D | soc_irq.S | 24 csrr t1, NDS_UCODE 31 sw t1, __soc_esf_t_ucode_OFFSET(a0) 41 lw t1, __soc_esf_t_ucode_OFFSET(a0) 48 csrw NDS_UCODE, t1
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D | start.S | 43 li t1, (1 << 19) 44 and t0, t0, t1 48 li t1, (1 << 20) 51 and t0, t0, t1
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/Zephyr-latest/soc/common/riscv-privileged/ |
D | soc_irq.S | 29 li t1, 1 30 sll t0, t1, a0 31 csrrc t1, mip, t0
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/Zephyr-latest/tests/subsys/fs/littlefs/src/ |
D | test_lfs_perf.c | 34 uint32_t t1; in write_read() local 95 t1 = k_uptime_get_32(); in write_read() 97 if (t1 == t0) { in write_read() 98 t1++; in write_read() 116 tag, nbuf, buf_size, total, (t1 - t0), in write_read() 117 (uint32_t)(total * 1000U / (t1 - t0)), in write_read() 118 (uint32_t)(total * 1000U / (t1 - t0) / 1024U)); in write_read() 134 t1 = k_uptime_get_32(); in write_read() 136 if (t1 == t0) { in write_read() 137 t1++; in write_read() [all …]
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/Zephyr-latest/soc/espressif/esp32c2/ |
D | soc_irq.S | 16 la t1, soc_intr_get_next_source 17 jalr ra, t1, 0
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/Zephyr-latest/soc/espressif/esp32c3/ |
D | soc_irq.S | 16 la t1, soc_intr_get_next_source 17 jalr ra, t1, 0
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/Zephyr-latest/samples/boards/nordic/coresight_stm/src/ |
D | main.c | 61 uint32_t t0, t1, t2, t3, t_s; in main() local 72 t1 = TEST_LOG(rpt, (LOG_INF("test with one argument %d", 100))); in main() 73 t1 -= delta; in main() 96 timing_report(t1, rpt, "log message with 1 argument"); in main()
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/Zephyr-latest/soc/espressif/esp32c6/ |
D | soc_irq.S | 22 la t1, soc_intr_get_next_source 23 jalr ra, t1, 0
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/Zephyr-latest/drivers/interrupt_controller/ |
D | intc_nuclei_eclic.S | 63 lw t1, RV_REGSIZE(t0) 66 jalr ra, t1, 0
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/Zephyr-latest/tests/boards/mtk_adsp/src/ |
D | main.c | 29 uint32_t t1 = k_cycle_get_32(), cc1 = ccount(); in cpu_hz() local 30 uint32_t hz = ((uint64_t)cc1 - cc0) * NOM_HZ / (t1 - t0); in cpu_hz()
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