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Searched refs:sys_clear_bit (Results 1 – 25 of 26) sorted by relevance

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/Zephyr-latest/drivers/gpio/
Dgpio_iproc.c57 sys_clear_bit(base + IPROC_GPIO_OUT_EN_OFFSET, pin); in gpio_iproc_configure()
132 sys_clear_bit(base + IPROC_GPIO_INT_TYPE_OFFSET, pin); in gpio_iproc_pin_interrupt_configure()
142 sys_clear_bit(base + IPROC_GPIO_INT_DE_OFFSET, pin); in gpio_iproc_pin_interrupt_configure()
146 sys_clear_bit(base + IPROC_GPIO_INT_DE_OFFSET, pin); in gpio_iproc_pin_interrupt_configure()
147 sys_clear_bit(base + IPROC_GPIO_INT_EDGE_OFFSET, pin); in gpio_iproc_pin_interrupt_configure()
151 sys_clear_bit(base + IPROC_GPIO_INT_MSTAT_OFFSET, pin); in gpio_iproc_pin_interrupt_configure()
Dgpio_stellaris.c99 sys_clear_bit(GPIO_REG_ADDR(base, GPIO_DIR_OFFSET), pin); in gpio_stellaris_configure()
104 sys_clear_bit(GPIO_REG_ADDR(base, GPIO_DEN_OFFSET), pin); in gpio_stellaris_configure()
211 sys_clear_bit(GPIO_REG_ADDR(base, GPIO_IS_OFFSET), pin); in gpio_stellaris_pin_interrupt_configure()
221 sys_clear_bit(GPIO_REG_ADDR(base, in gpio_stellaris_pin_interrupt_configure()
225 sys_clear_bit(GPIO_REG_ADDR(base, GPIO_IM_OFFSET), pin); in gpio_stellaris_pin_interrupt_configure()
Dgpio_brcmstb.c46 sys_clear_bit(data->base + GIO_IODIR, pin); in gpio_brcmstb_pin_configure()
51 sys_clear_bit(data->base + GIO_DATA, pin); in gpio_brcmstb_pin_configure()
Dgpio_rp1.c100 sys_clear_bit(RIO_OUT_CLR(data->rio_base), pin); in gpio_rp1_pin_configure()
103 sys_clear_bit(RIO_OUT_SET(data->rio_base), pin); in gpio_rp1_pin_configure()
Dgpio_dw.c74 sys_clear_bit(base_addr + offset, bit); in dw_set_bit()
/Zephyr-latest/include/zephyr/arch/common/
Dsys_bitops.h31 static ALWAYS_INLINE void sys_clear_bit(mem_addr_t addr, unsigned int bit) in sys_clear_bit() function
71 sys_clear_bit(addr + ((bit >> 5) << 2), bit & 0x1F); in sys_bitfield_clear_bit()
97 sys_clear_bit(addr, bit); in sys_test_and_clear_bit()
/Zephyr-latest/drivers/counter/
Dcounter_dw_timer.c120 sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT); in counter_dw_timer_start()
123 sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_MODE_BIT); in counter_dw_timer_start()
137 sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT); in counter_dw_timer_disable()
194 sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_INTR_MASK_BIT); in counter_dw_timer_set_top_value()
201 sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT); in counter_dw_timer_set_top_value()
254 sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT); in counter_dw_timer_set_alarm()
258 sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_INTR_MASK_BIT); in counter_dw_timer_set_alarm()
/Zephyr-latest/drivers/pwm/
Dpwm_sifive.c93 sys_clear_bit(PWM_REG(config, REG_PWMCFG), SF_PWMSTICKY); in pwm_sifive_init()
94 sys_clear_bit(PWM_REG(config, REG_PWMCFG), SF_PWMDEGLITCH); in pwm_sifive_init()
102 sys_clear_bit(PWM_REG(config, REG_PWMCFG), SF_PWMCMPCENTER(i)); in pwm_sifive_init()
103 sys_clear_bit(PWM_REG(config, REG_PWMCFG), SF_PWMCMPGANG(i)); in pwm_sifive_init()
/Zephyr-latest/drivers/spi/
Dspi_sifive.c59 sys_clear_bit(SPI_REG(dev, REG_SCKMODE), SF_SCKMODE_POL); in spi_config()
71 sys_clear_bit(SPI_REG(dev, REG_SCKMODE), SF_SCKMODE_PHA); in spi_config()
98 sys_clear_bit(SPI_REG(dev, REG_FMT), SF_FMT_ENDIAN); in spi_config()
182 sys_clear_bit(SPI_REG(dev, REG_FCTRL), SF_FCTRL_EN); in spi_sifive_init()
Dspi_gecko_usart.c153 sys_clear_bit(ctrl_reg, _USART_CTRL_CSINV_SHIFT); in spi_config()
163 sys_clear_bit(ctrl_reg, _USART_CTRL_MSBF_SHIFT); in spi_config()
Dspi_dw.h131 sys_clear_bit(addr + off, bit); in reg_clear_bit()
/Zephyr-latest/drivers/reset/
Dreset_gd32.c48 sys_clear_bit(config->base + GD32_RESET_ID_OFFSET(id), in reset_gd32_line_deassert()
Dreset_numaker.c49 sys_clear_bit(config->base + NUMAKER_RESET_IP_OFFSET(id), NUMAKER_RESET_IP_BIT(id)); in reset_numaker_line_deassert()
Dreset_stm32.c51 sys_clear_bit(config->base + STM32_RESET_SET_OFFSET(id), in reset_stm32_line_deassert()
Dreset_intel_socfpga.c57 sys_clear_bit(base_address + offset, regbit); in reset_intel_soc_update()
/Zephyr-latest/include/zephyr/arch/x86/
Darch.h163 static ALWAYS_INLINE void sys_clear_bit(mem_addr_t addr, unsigned int bit) in sys_clear_bit() function
209 #define sys_bitfield_clear_bit sys_clear_bit
/Zephyr-latest/drivers/i2c/
Di2c_dw.h136 #define Z_REG_CLEAR_BIT sys_clear_bit
Di2c_bcm_iproc.c203 sys_clear_bit(base + CFG_OFFSET, CFG_RESET_SHIFT); in iproc_i2c_reset_controller()
598 sys_clear_bit(base + TIM_CFG_OFFSET, TIM_CFG_MODE_400_SHIFT); in iproc_i2c_configure()
644 sys_clear_bit(base + IE_OFFSET, IS_M_RX_THLD_SHIFT); in iproc_i2c_data_recv()
/Zephyr-latest/tests/kernel/common/src/
Dbitfield.c55 sys_clear_bit((mem_addr_t)&b1, bit); in ZTEST()
/Zephyr-latest/drivers/sdhc/
Dsdhc_cdns_ll.c376 sys_clear_bit(cdns_params.reg_base + SDHC_CDNS_HRS09, 0); in sdhc_cdns_host_set_clk()
400 sys_clear_bit(cdns_params.reg_base + SDHC_CDNS_SRS10, WIDTH_BIT1); in sdhc_cdns_set_ios()
513 sys_clear_bit(cdns_params.reg_base + SDHC_CDNS_HRS09, 0); in sdhc_cdns_set_clk()
548 sys_clear_bit(cdns_params.reg_base + SDHC_CDNS_HRS09, CDNS_HRS09_PHY_SW_RESET); in sdhc_cdns_reset()
/Zephyr-latest/drivers/clock_control/
Dclock_control_gd32.c88 sys_clear_bit(config->base + GD32_CLOCK_ID_OFFSET(id), in clock_control_gd32_off()
/Zephyr-latest/drivers/pcie/endpoint/
Dpcie_ep_iproc_msi.c155 sys_clear_bit(PBA_OFFSET(msix_num), PENDING_BIT(msix_num)); in generate_pending_msix()
/Zephyr-latest/drivers/interrupt_controller/
Dintc_gicv3.c316 sys_clear_bit(rdist + GICR_PWRR, GICR_PWRR_RDPD); in gicv3_rdist_enable()
323 sys_clear_bit(rdist + GICR_WAKER, GICR_WAKER_PS); in gicv3_rdist_enable()
/Zephyr-latest/drivers/dma/
Ddma_dw_axi.c731 sys_clear_bit(reg_base + DMA_DW_AXI_CHENREG, channel); in dma_dw_axi_stop()
/Zephyr-latest/drivers/flash/
Dflash_cadence_nand_ll.c277 sys_clear_bit(CNF_MINICTRL(base_address, DLL_PHY_CTRL), CNF_DLL_PHY_RST_N); in cdns_nand_set_opr_mode()

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