Home
last modified time | relevance | path

Searched refs:r1 (Results 1 – 25 of 79) sorted by relevance

1234

/Zephyr-latest/arch/arm/core/cortex_a_r/
Dreset.S95 mov r1, #0
165 fmdrr d0, r1, r1
166 fmdrr d1, r1, r1
167 fmdrr d2, r1, r1
168 fmdrr d3, r1, r1
169 fmdrr d4, r1, r1
170 fmdrr d5, r1, r1
171 fmdrr d6, r1, r1
172 fmdrr d7, r1, r1
173 fmdrr d8, r1, r1
[all …]
Disr_wrapper.S170 movs r1, #0
172 str r1, [r2, #_kernel_offset_to_idle]
184 push {r0, r1}
202 mov r1, #CONFIG_NUM_IRQS
203 lsl r1, r1, #3
204 cmp r0, r1
207 ldr r1, =_sw_isr_table
208 add r1, r1, r0 /* table entry: ISRs must have their MSB set to stay
211 ldm r1!,{r0,r3} /* arg in r0, ISR in r3 */
216 pop {r0, r1}
[all …]
Dexc.S59 vmrs r1, fpexc
69 stm r2, {r0, r1}
79 sub r1, sp, #___callee_saved_t_SIZEOF
80 str r1, [sp]
82 stm r1, {r4-r11, sp}
86 mov sp, r1
93 ldr r1, [r2, #___cpu_t_nested_OFFSET]
94 add r1, r1, #1
95 str r1, [r2, #___cpu_t_nested_OFFSET]
135 ldr r1, [r2, #___cpu_t_nested_OFFSET]
[all …]
Dexc_exit.S34 push {r0-r1}
44 pop {r0-r1}
48 str r1, [sp, #12]
51 and r1, #MODE_MASK
52 cmp r1, #MODE_USR
62 pop {r0-r1}
73 ldr r1, [r2, #___cpu_t_fp_ctx_OFFSET]
74 cmp r1, #0
82 moveq r1, #0
83 streq r1, [r2, #___cpu_t_fp_ctx_OFFSET]
[all …]
Dswitch.S39 add r2, r1, r2
46 strb r3, [r1, #_thread_offset_to_exception_depth]
59 str r1, [r1, #___thread_t_switch_handle_OFFSET]
108 ldreq r1, [lr, #-4]
109 biceq r1, #0xff000000
112 ldr r1, [lr, #-2]
113 and r1, #0xff
125 cmp r1, #_SVC_CALL_RUNTIME_EXCEPT
129 cmp r1, #_SVC_CALL_IRQ_OFFLOAD
157 mov r1, #0
[all …]
Dswap_helper.S54 get_cpu r1
55 ldr r2, [r1, #___cpu_t_current_OFFSET]
85 ldr r0, [r1, #___cpu_t_fp_ctx_OFFSET]
110 str r0, [r1, #___cpu_t_fp_ctx_OFFSET]
117 str r2, [r1, #___cpu_t_current_OFFSET]
297 ldreq r1, [lr, #-4]
298 biceq r1, #0xff000000
301 ldr r1, [lr, #-2]
302 and r1, #0xff
314 cmp r1, #_SVC_CALL_SYSTEM_CALL
[all …]
/Zephyr-latest/arch/arm/core/
Duserspace.S55 mov ip, r1
56 ldr r1, =_thread_offset_to_priv_stack_start
57 ldr r0, [r0, r1] /* priv stack ptr */
58 ldr r1, =CONFIG_PRIVILEGED_STACK_SIZE
59 add r0, r0, r1
61 mov r1, ip
111 push {r1,r2,r3,lr}
113 mov r1, ip
114 push {r0,r1}
162 ldr r1,=0xaaaaaaaa
[all …]
/Zephyr-latest/arch/arc/core/
Dcpu_idle.S47 ld r1, [z_arc_cpu_sleep_mode]
48 or r1, r1, (1 << 4) /* set IRQ-enabled bit */
49 sleep r1
72 ld r1, [z_arc_cpu_sleep_mode]
73 or r1, r1, (1 << 4) /* set IRQ-enabled bit */
74 sleep r1
Dreset.S110 mov_s r1, 1
111 sr r1, [_ARC_V2_DC_IVDC]
133 mov_s r1, ARC_MPU_EN_RESET_VALUE
134 sr r1, [_ARC_V2_MPU_EN]
139 mov_s r1, 0
145 sr r1, [_ARC_V2_MPU_RSTART]
146 sr r1, [_ARC_V2_MPU_REND]
147 sr r1, [_ARC_V2_MPU_RPER]
158 lr r1, [_ARC_HW_PF_CTRL]
159 or r1, r1, _ARC_HW_PF_CTRL_ENABLE
[all …]
Dfast_irq.S78 _check_and_inc_int_nest_counter r0, r1
94 lr r1, [_ARC_V2_STATUS32]
95 and r1, r1, ~_ARC_V2_STATUS32_RB(7)
96 kflag r1
142 _dec_int_nest_counter r0, r1
144 _check_nest_int_by_irq_act r0, r1
182 _get_curr_cpu_irq_stack r1
183 st r0, [r1, -4]
184 st r2, [r1, -8]
236 _get_curr_cpu_irq_stack r1
[all …]
Duserspace.S17 mov_s r1, 0
65 pop_s r1
73 st.aw r1, [r5, -4]
108 push_s r1
147 mov_s r1, z_thread_entry_wrapper1
150 sr r1, [_ARC_V2_ERET]
204 ld_s r1, [sp, ___isf_t_r1_OFFSET]
258 add_s r1, r1, 1
259 mov lp_count, r1
264 ldb.aw r1, [r12, 1]
[all …]
/Zephyr-latest/soc/nxp/mcx/mcxw/
Dmcxw71_platform_init.S25 ldr r1, =.ram_init_ctcm01
26 bics r1, #0x10000000
27 cmp r0, r1
31 ldr r1, =0x14004000
38 cmp r0, r1
42 ldr r1, =0x30010000
45 cmp r0, r1
49 ldr r1, =0x3001c000
52 cmp r0, r1
/Zephyr-latest/soc/nxp/kinetis/kv5x/
Dwdog.S54 movw r1, #WDOG_UNLOCK_1_CMD
55 strh r1, [r0, #WDOG_UNLOCK_OFFSET]
57 movw r1, #WDOG_UNLOCK_2_CMD
58 strh r1, [r0, #WDOG_UNLOCK_OFFSET]
67 ldrh r1, [r0, #WDOG_SCTRL_HI_OFFSET]
69 bics r1, r2
70 strh r1, [r0, #WDOG_SCTRL_HI_OFFSET]
/Zephyr-latest/arch/arm/core/cortex_m/
Dswap_helper.S62 pop {r0, r1}
63 mov lr, r1
70 ldr r1, =_kernel
71 ldr r2, [r1, #_kernel_offset_to_current]
144 ldr r2, [r1, #_kernel_offset_to_ready_q_cache]
146 str r2, [r1, #_kernel_offset_to_current]
226 movs.n r1, #1
227 bics r3, r1
334 pop {r0, r1}
335 mov lr, r1
[all …]
Dirq_relay.S36 ldr r1, =_vector_table_pointer;
37 ldr r1, [r1];
38 adds r1, r1, r0;
39 ldr r1, [r1];
48 bx r1;
Dreset.S74 ldr r1, =z_sys_post_kernel
75 strb r0, [r1]
104 ldr r1, =_SCS_MPU_CTRL
105 str r0, [r1]
140 ldr r1, =0xaa
150 ldr r1, =CONFIG_ISR_STACK_SIZE + MPU_GUARD_ALIGN_AND_SIZE
151 adds r0, r0, r1
154 movs r1, #2
155 orrs r0, r1 /* CONTROL_SPSEL_Msk */
Dpm_s2ram.S56 mov r1, r8; \
61 push {r1-r5, lr}
77 pop {r1-r6}; \
83 mov r8, r1; \
174 ldr r1, =_cpu_context
176 SAVE_SPECIAL_REGISTERS(/* ctx: */ r1, /* tmp: */ r2)
181 mov r1, lr
183 mov lr, r1
202 mov r1, lr
204 mov lr, r1
[all …]
/Zephyr-latest/soc/ti/lm3s6965/
Dreboot.S22 ldr r1, =0xe000e000
23 str r0, [r1, #0xd08] /* VTOR */
33 ldr r1, =_SCS_ICSR
34 ldr r1, [r1]
35 ands.w r0, r1
50 ldr r1, =0xfffffffe
51 and.w r2, r1
/Zephyr-latest/soc/nxp/s32/s32k3/
Ds32k3xx_startup.S31 ldr r1, =MC_RGM_BASE
32 ldr r2, [r1, MC_RGM_DES]
35 ldr r2, [r1, MC_RGM_FES]
40 ldr r1, = DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
51 stm r1!, {r0,r3}
59 ldr r1, = DT_REG_ADDR(DT_CHOSEN(zephyr_itcm))
65 stm r1!, {r0,r3}
72 ldr r1, = DT_REG_ADDR(DT_CHOSEN(zephyr_dtcm))
78 stm r1!, {r0,r3}
/Zephyr-latest/arch/nios2/core/
Dcrt0.S64 movhi r1, %hi(__start)
65 ori r1, r1, %lo(__start)
66 jmp r1
107 movhi r1, %hi(z_interrupt_stacks)
108 ori r1, r1, %lo(z_interrupt_stacks)
117 stw r3, (r1)
119 addi r1, r1, 4
/Zephyr-latest/include/zephyr/arch/arm/
Dsyscall.h45 register uint32_t r1 __asm__("r1") = arg2; in arch_syscall_invoke6()
53 : "=r"(ret), "=r"(r1), "=r"(r2), "=r"(r3) in arch_syscall_invoke6()
55 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in arch_syscall_invoke6()
68 register uint32_t r1 __asm__("r1") = arg2; in arch_syscall_invoke5()
75 : "=r"(ret), "=r"(r1), "=r"(r2), "=r"(r3) in arch_syscall_invoke5()
77 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in arch_syscall_invoke5()
89 register uint32_t r1 __asm__("r1") = arg2; in arch_syscall_invoke4()
95 : "=r"(ret), "=r"(r1), "=r"(r2), "=r"(r3) in arch_syscall_invoke4()
97 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in arch_syscall_invoke4()
109 register uint32_t r1 __asm__("r1") = arg2; in arch_syscall_invoke3()
[all …]
/Zephyr-latest/scripts/coccinelle/
Dreturnvar.cocci39 @r1 depends on (report || org) && !(file in "ext")@
51 p1 << r1.p1;
52 p2 << r1.p2;
53 C << r1.C;
54 ret << r1.ret;
61 p1 << r1.p1;
62 p2 << r1.p2;
63 C << r1.C;
64 ret << r1.ret;
Dsemicolon.cocci46 @r1 depends on !(file in "ext")@
59 p << r1.p;
60 p1 << r1.p1;
66 position r1.p;
71 p << r1.p;
76 position r1.p;
81 p << r1.p;
/Zephyr-latest/soc/nxp/lpc/lpc54xxx/gcc/
Dstartup_LPC54114_cm4.S51 ldr r1, [r0] /* r1 = CPU ID status */
52 lsrs r1, r1, #4 /* Right justify 12 CPU ID bits */
54 ands r2, r1, r2 /* r2 = ARM COrtex CPU ID */
85 ldr r1, [r0] /* r5 = SYSCON co-processor stack address */
87 mov sp, r1 /* Update slave CPU stack pointer */
/Zephyr-latest/include/zephyr/arch/arm64/
Dsyscall.h45 register uint64_t r1 __asm__("x1") = arg2; in arch_syscall_invoke6()
55 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in arch_syscall_invoke6()
68 register uint64_t r1 __asm__("x1") = arg2; in arch_syscall_invoke5()
77 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in arch_syscall_invoke5()
89 register uint64_t r1 __asm__("x1") = arg2; in arch_syscall_invoke4()
97 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in arch_syscall_invoke4()
109 register uint64_t r1 __asm__("x1") = arg2; in arch_syscall_invoke3()
116 "r" (ret), "r" (r1), "r" (r2), "r" (r8) in arch_syscall_invoke3()
126 register uint64_t r1 __asm__("x1") = arg2; in arch_syscall_invoke2()
132 "r" (ret), "r" (r1), "r" (r8) in arch_syscall_invoke2()

1234