1/*
2 * Copyright 2023 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <zephyr/devicetree.h>
8#include <zephyr/toolchain.h>
9#include <zephyr/linker/sections.h>
10
11#define MC_RGM_BASE 0x4028C000
12#define MC_RGM_DES  0x0
13#define MC_RGM_FES  0x8
14
15_ASM_FILE_PROLOGUE
16
17GTEXT(soc_reset_hook)
18
19SECTION_FUNC(TEXT, soc_reset_hook)
20
21	/*
22	 * On destructive reset, SRAM and TCM memories must be initialized to a known value using a
23	 * 64-bit master before 32-bit masters can read or write to them. Note that SRAM retains
24	 * content during functional reset through a hardware mechanism, therefore accesses do not
25	 * cause any content corruption errors.
26	 *
27	 * This is implemented directly in ASM, to ensure no stack access is performed.
28	 */
29
30	/* If we come from a destructive reset, then ignore functional reset flags */
31	ldr r1, =MC_RGM_BASE
32	ldr r2, [r1, MC_RGM_DES]
33	cmp r2, 0x0
34	bne ECC_INIT
35	ldr r2, [r1, MC_RGM_FES]
36	cmp r2, 0x0
37	bne ECC_END
38
39ECC_INIT:
40	ldr r1, = DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
41	ldr r2, = DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
42
43	subs	r2, #1
44
45	ble SRAM_LOOP_END
46
47	movs	r0, 0
48	movs	r3, 0
49
50SRAM_LOOP:
51	stm r1!, {r0,r3}
52	subs r2, 8
53	bge SRAM_LOOP
54
55SRAM_LOOP_END:
56
57#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)
58
59	ldr r1, = DT_REG_ADDR(DT_CHOSEN(zephyr_itcm))
60	ldr r2, = DT_REG_SIZE(DT_CHOSEN(zephyr_itcm))
61
62	subs	r2, #1
63
64ITCM_LOOP:
65	stm r1!, {r0,r3}
66	subs r2, 8
67	bge ITCM_LOOP
68#endif
69
70#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)
71
72	ldr r1, = DT_REG_ADDR(DT_CHOSEN(zephyr_dtcm))
73	ldr r2, = DT_REG_SIZE(DT_CHOSEN(zephyr_dtcm))
74
75	subs	r2, #1
76
77DTCM_LOOP:
78	stm r1!, {r0,r3}
79	subs r2, 8
80	bge DTCM_LOOP
81#endif
82
83ECC_END:
84	bx lr
85