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Searched refs:pte (Results 1 – 4 of 4) sorted by relevance

/Zephyr-latest/arch/xtensa/include/
Dxtensa_mmu_priv.h74 #define XTENSA_MMU_PTE_ATTR_GET(pte) \ argument
75 ((pte) & XTENSA_MMU_PTE_ATTR_MASK)
78 #define XTENSA_MMU_PTE_ATTR_SET(pte, attr) \ argument
79 (((pte) & ~XTENSA_MMU_PTE_ATTR_MASK) | (attr & XTENSA_MMU_PTE_ATTR_MASK))
82 #define XTENSA_MMU_PTE_SW_SET(pte, sw) \ argument
83 (((pte) & ~XTENSA_MMU_PTE_SW_MASK) | (sw << XTENSA_MMU_PTE_SW_SHIFT))
86 #define XTENSA_MMU_PTE_SW_GET(pte) \ argument
87 (((pte) & XTENSA_MMU_PTE_SW_MASK) >> XTENSA_MMU_PTE_SW_SHIFT)
90 #define XTENSA_MMU_PTE_RING_SET(pte, ring) \ argument
91 (((pte) & ~XTENSA_MMU_PTE_RING_MASK) | \
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/Zephyr-latest/arch/arm64/core/
Dmmu.c61 static inline unsigned int table_index(uint64_t *pte) in table_index() argument
63 unsigned int i = (pte - xlat_tables) / Ln_XLAT_NUM_ENTRIES; in table_index()
65 __ASSERT(i < CONFIG_MAX_XLAT_TABLES, "table %p out of range", pte); in table_index()
194 static void debug_show_pte(uint64_t *pte, unsigned int level) in debug_show_pte() argument
197 MMU_DEBUG("[%d]%p: ", table_index(pte), pte); in debug_show_pte()
199 if (is_free_desc(*pte)) { in debug_show_pte()
204 MMU_DEBUG("0x%016llx ", *pte); in debug_show_pte()
206 if (is_table_desc(*pte, level)) { in debug_show_pte()
207 uint64_t *table = pte_desc_table(*pte); in debug_show_pte()
213 if (is_block_desc(*pte)) { in debug_show_pte()
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/Zephyr-latest/arch/xtensa/core/
Dptables.c176 static inline bool is_pte_illegal(uint32_t pte) in is_pte_illegal() argument
178 uint32_t attr = pte & XTENSA_MMU_PTE_ATTR_MASK; in is_pte_illegal()
225 uint32_t pte = XTENSA_MMU_PTE(page, in map_memory_range() local
246 table[l2_pos] = pte; in map_memory_range()
850 uint32_t *l2_table, pte; in region_map_update() local
861 pte = XTENSA_MMU_PTE_RING_SET(l2_table[l2_pos], ring); in region_map_update()
862 pte = XTENSA_MMU_PTE_ATTR_SET(pte, flags); in region_map_update()
864 l2_table[l2_pos] = pte; in region_map_update()
1049 uint32_t rasid, pte, *l2_table; in page_validate() local
1058 pte = l2_table[l2_pos]; in page_validate()
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/Zephyr-latest/arch/x86/core/
Dx86_mmu.c400 static inline bool is_flipped_pte(pentry_t pte) in is_flipped_pte() argument
402 return (pte & MMU_P) == 0 && (pte & PTE_ZERO) != 0; in is_flipped_pte()
930 static inline pentry_t pte_atomic_update(pentry_t *pte, pentry_t update_val, in pte_atomic_update() argument
940 old_val = atomic_pte_get(pte); in pte_atomic_update()
960 } while (atomic_pte_cas(pte, old_val, new_val) == false); in pte_atomic_update()
2069 pentry_t pte = 0; in arch_page_phys_get() local
2075 pentry_get(&level, &pte, z_x86_page_tables_get(), virt); in arch_page_phys_get()
2077 if ((pte & MMU_P) != 0) { in arch_page_phys_get()
2079 *phys = (uintptr_t)get_entry_phys(pte, PTE_LEVEL); in arch_page_phys_get()
2207 pentry_t pte; in arch_page_location_get() local
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