Searched refs:pllm (Results 1 – 6 of 6) sorted by relevance
| /Zephyr-latest/drivers/clock_control/ |
| D | clock_stm32f2_f4_f7.c | 103 pllm(STM32_PLL_M_DIVISOR), in config_pll_sysclock()
110 pllm(STM32_PLL_M_DIVISOR), in config_pll_sysclock()
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| D | clock_stm32g4.c | 66 pllm(STM32_PLL_M_DIVISOR), in config_pll_sysclock()
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| D | clock_stm32g0_u0.c | 62 pllm(STM32_PLL_M_DIVISOR), in config_pll_sysclock()
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| D | clock_stm32l4_l5_wb_wl.c | 81 pllm(STM32_PLL_M_DIVISOR), in config_pll_sysclock()
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| D | clock_stm32_ll_common.h | 19 #define pllm(v) z_pllm(v) macro
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| D | clock_stm32_ll_h7.c | 997 uint32_t sysclk, hsivalue, pllsource, pllm, pllp, core_presc; local
1021 pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos);
1030 if (pllm != 0U) {
1033 pllvco = ((float_t)HSE_VALUE / (float_t)pllm) *
1039 pllvco = ((float_t)CSI_VALUE / (float_t)pllm) *
1048 pllvco = ((float_t)hsivalue / (float_t)pllm) *
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