| /Zephyr-latest/drivers/can/ |
| D | can_common.c | 158 uint16_t tseg1_max = max->phase_seg1 + max->prop_seg; in update_sample_pnt()
159 uint16_t tseg1_min = min->phase_seg1 + min->prop_seg; in update_sample_pnt()
191 res->phase_seg1 = tseg1 - res->prop_seg; in update_sample_pnt()
193 if (res->phase_seg1 > max->phase_seg1) { in update_sample_pnt()
195 res->phase_seg1 = max->phase_seg1; in update_sample_pnt()
196 res->prop_seg = tseg1 - res->phase_seg1; in update_sample_pnt()
197 } else if (res->phase_seg1 < min->phase_seg1) { in update_sample_pnt()
199 res->phase_seg1 = min->phase_seg1; in update_sample_pnt()
200 res->prop_seg = tseg1 - res->phase_seg1; in update_sample_pnt()
255 uint32_t total_tq = CAN_SYNC_SEG + max->prop_seg + max->phase_seg1 + max->phase_seg2; in can_calc_timing_internal()
[all …]
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| D | can_fake.c | 126 .phase_seg1 = 2,
133 .phase_seg1 = 256,
143 .phase_seg1 = 1,
150 .phase_seg1 = 32,
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| D | can_loopback.c | 385 .phase_seg1 = 2,
392 .phase_seg1 = 256,
402 .phase_seg1 = 1,
409 .phase_seg1 = 32,
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| D | can_mcux_flexcan.c | 295 timing.phaseSeg1 = data->timing.phase_seg1 - 1U; in mcux_flexcan_start()
304 timing.fphaseSeg1 = data->timing_data.phase_seg1 - 1U; in mcux_flexcan_start()
1155 data->timing.prescaler, data->timing.phase_seg1, in mcux_flexcan_init()
1176 data->timing_data.prescaler, data->timing_data.phase_seg1, in mcux_flexcan_init()
1205 (1U + data->timing.prop_seg + data->timing.phase_seg1 + in mcux_flexcan_init()
1211 (1U + data->timing_data.prop_seg + data->timing_data.phase_seg1 + in mcux_flexcan_init()
1224 flexcan_config.timingConfig.phaseSeg1 = data->timing.phase_seg1 - 1U; in mcux_flexcan_init()
1231 flexcan_config.timingConfig.fphaseSeg1 = data->timing_data.phase_seg1 - 1U; in mcux_flexcan_init()
1288 .phase_seg1 = 0x01,
1295 .phase_seg1 = 0x08,
[all …]
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| D | can_shell.c | 400 timing_min->phase_seg1, timing_max->phase_seg1, in cmd_can_show()
412 timing_min->phase_seg1, timing_max->phase_seg1, in cmd_can_show()
485 timing.sjw, timing.prop_seg, timing.phase_seg1, timing.phase_seg2, in cmd_can_bitrate_set()
556 timing.sjw, timing.prop_seg, timing.phase_seg1, timing.phase_seg2, in cmd_can_dbitrate_set()
594 timing->phase_seg1 = (uint32_t)strtoul(argv[4], &endptr, 10); in can_shell_parse_timing()
632 "prescaler %u", timing.sjw, timing.prop_seg, timing.phase_seg1, in cmd_can_timing_set()
661 "phase_seg2 %u, prescaler %u", timing.sjw, timing.prop_seg, timing.phase_seg1, in cmd_can_dtiming_set()
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| D | can_native_linux.c | 418 .phase_seg1 = 0x01,
425 .phase_seg1 = 0x0F,
434 .phase_seg1 = 0x01,
441 .phase_seg1 = 0x0F,
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| D | can_esp32_twai.c | 132 btr1 = TWAI_TIME_SEG1_PREP(timing->phase_seg1 - 1) | in can_esp32_twai_set_timing()
247 .phase_seg1 = 0x10,
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| D | can_mcp251xfd.c | 425 timing->prop_seg + timing->phase_seg1 - 1); in mcp251xfd_set_timing()
463 timing->prop_seg + timing->phase_seg1 - 1); in mcp251xfd_set_timing_data()
1586 LOG_DBG("Presc: %d, BS1: %d, BS2: %d", timing.prescaler, timing.phase_seg1, in mcp251xfd_init()
1599 timing_data.phase_seg1, timing_data.phase_seg2); in mcp251xfd_init()
1704 .phase_seg1 = 2,
1711 .phase_seg1 = 256,
1719 .phase_seg1 = 1,
1726 .phase_seg1 = 32,
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| D | can_nxp_s32_canxl.c | 692 timing->prop_seg, timing->phase_seg1, timing->phase_seg2, in nxp_s32_zcan_timing_to_canxl_timing()
696 canxl_timing->phaseSeg1 = timing->phase_seg1 - 1U; in nxp_s32_zcan_timing_to_canxl_timing()
1102 .phase_seg1 = 0x01,
1109 .phase_seg1 = 0x08,
1118 .phase_seg1 = 0x01,
1125 .phase_seg1 = 0x08,
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| D | can_renesas_ra.c | 23 .phase_seg1 = 255, \
32 .phase_seg1 = 2, \
42 .phase_seg1 = 31, \
50 .phase_seg1 = 2, \
196 .time_segment_1 = z_timing->prop_seg + z_timing->phase_seg1, in set_hw_timing_configuration()
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| D | can_mcp2515.c | 346 const uint8_t phseg1 = (timing->phase_seg1 - 1) << 3; in mcp2515_set_timing()
896 .phase_seg1 = 0x01,
903 .phase_seg1 = 0x08,
983 timing.prescaler, timing.phase_seg1, timing.phase_seg2); in mcp2515_init()
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| D | can_xmc4xxx.c | 133 reg |= FIELD_PREP(CAN_NODE_NBTR_TSEG1_Msk, timing->prop_seg + timing->phase_seg1 - 1); in can_xmc4xxx_set_timing()
878 LOG_DBG("Presc: %d, BS1: %d, BS2: %d", timing.prescaler, timing.phase_seg1, in can_xmc4xxx_init()
901 .phase_seg1 = 3,
908 .phase_seg1 = 16,
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| D | can_rcar.c | 728 bcr = RCAR_CAN_BCR_TSEG1(timing->phase_seg1 + timing->prop_seg - 1) | in can_rcar_set_bittiming()
1086 timing.prescaler, timing.phase_seg1, timing.phase_seg2); in can_rcar_init()
1172 .phase_seg1 = 0x04,
1179 .phase_seg1 = 0x10,
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| D | can_stm32_bxcan.c | 556 (((timing->phase_seg1 - 1) << CAN_BTR_TS1_Pos) & CAN_BTR_TS1_Msk) | in can_stm32_set_timing()
669 timing.prescaler, timing.phase_seg1, timing.phase_seg2); in can_stm32_init()
1085 .phase_seg1 = 0x01,
1092 .phase_seg1 = 0x10,
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| D | can_mcan.c | 210 FIELD_PREP(CAN_MCAN_NBTP_NTSEG1, timing->phase_seg1 - 1UL) | in can_mcan_set_timing()
241 FIELD_PREP(CAN_MCAN_DBTP_DTSEG1, timing_data->phase_seg1 - 1UL) | in can_mcan_set_timing_data()
1476 LOG_DBG("Presc: %d, TS1: %d, TS2: %d", timing.prescaler, timing.phase_seg1, in can_mcan_init()
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| D | can_sja1000.c | 122 btr1 = CAN_SJA1000_BTR1_TSEG1_PREP(timing->phase_seg1 - 1) | in can_sja1000_set_timing()
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| /Zephyr-latest/tests/drivers/can/timing/src/ |
| D | main.c | 78 const uint32_t ts = 1 + timing->prop_seg + timing->phase_seg1 + timing->phase_seg2; in assert_bitrate_correct()
107 zassert_true(timing->phase_seg1 <= max->phase_seg1, "phase_seg1 exceeds max"); in assert_timing_within_bounds()
113 zassert_true(timing->phase_seg1 >= min->phase_seg1, "phase_seg1 lower than min"); in assert_timing_within_bounds()
130 const uint32_t ts = 1 + timing->prop_seg + timing->phase_seg1 + timing->phase_seg2; in assert_sp_within_margin()
131 const uint16_t sp_calc = ((1 + timing->prop_seg + timing->phase_seg1) * 1000) / ts; in assert_sp_within_margin()
183 timing.sjw, timing.prop_seg, timing.phase_seg1, timing.phase_seg2, in test_timing_values()
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| /Zephyr-latest/include/zephyr/drivers/can/ |
| D | can_sja1000.h | 66 .phase_seg1 = 1, \
78 .phase_seg1 = 16, \
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| D | can_mcan.h | 855 .phase_seg1 = 2, \
867 .phase_seg1 = 256, \
879 .phase_seg1 = 1, \
891 .phase_seg1 = 32, \
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| /Zephyr-latest/tests/drivers/can/shell/src/ |
| D | main.c | 36 zassert_equal(t1->phase_seg1, t2->phase_seg1, "hase_seg1 mismatch"); in assert_can_timing_equal()
217 .phase_seg1 = 217U, in ZTEST()
249 .phase_seg1 = 29U, in ZTEST()
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| /Zephyr-latest/include/zephyr/drivers/ |
| D | can.h | 268 uint16_t phase_seg1; member
328 CLAMP((1U + _timing_data->prop_seg + _timing_data->phase_seg1) * _timing_data->prescaler, \
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| /Zephyr-latest/doc/hardware/peripherals/can/ |
| D | shell.rst | 79 … timing: sjw 1..128, prop_seg 0..0, phase_seg1 2..256, phase_seg2 2..128, prescaler 1..512
80 timing data: sjw 1..16, prop_seg 0..0, phase_seg1 1..32, phase_seg2 1..16, prescaler 1..32
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