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Searched refs:memory_regions (Results 1 – 17 of 17) sorted by relevance

/Zephyr-latest/drivers/coredump/
Dcoredump_impl.c25 size_t memory_regions[]; member
43 uintptr_t start_address = config->memory_regions[0]; in coredump_impl_dump()
44 size_t size = config->memory_regions[1]; in coredump_impl_dump()
58 uintptr_t start_address = config->memory_regions[i]; in coredump_impl_dump()
59 size_t size = config->memory_regions[i+1]; in coredump_impl_dump()
144 BUILD_ASSERT(DT_INST_PROP_LEN(n, memory_regions) == 2, \
146 BUILD_ASSERT(DT_INST_PROP_BY_IDX(n, memory_regions, 0) == 0, \
148 static uint8_t coredump_bytes[DT_INST_PROP_BY_IDX(n, memory_regions, 1)] \
154 COND_CODE_1(DT_INST_NODE_HAS_PROP(n, memory_regions), \
156 .length = DT_INST_PROP_LEN(n, memory_regions), \
[all …]
/Zephyr-latest/soc/nordic/common/
Ddmm.h50 #define DMM_ALIGN_SIZE(node_id) DMM_REG_ALIGN_SIZE(DT_PHANDLE(node_id, memory_regions))
60 COND_CODE_1(DT_NODE_HAS_PROP(node_id, memory_regions), \
61 ((void *)DT_REG_ADDR(DT_PHANDLE(node_id, memory_regions))), (NULL))
69 COND_CODE_1(DT_NODE_HAS_PROP(node_id, memory_regions), \
71 DT_PHANDLE(node_id, memory_regions))))) \
/Zephyr-latest/tests/drivers/coredump/coredump_api/src/
Dmain.c50 uint32_t expected_size = DT_PROP_BY_IDX(DT_NODELABEL(coredump_devicecb), memory_regions, 1); in test_coredump_callback()
64 (uint32_t *)DT_PROP_BY_IDX(DT_NODELABEL(coredump_device0), memory_regions, 0); in coredump_tests_suite_setup()
66 (uint32_t *)DT_PROP_BY_IDX(DT_NODELABEL(coredump_device0), memory_regions, 2); in coredump_tests_suite_setup()
68 (uint32_t *)DT_PROP_BY_IDX(DT_NODELABEL(coredump_device1), memory_regions, 0); in coredump_tests_suite_setup()
/Zephyr-latest/tests/boards/nrf/dmm/src/
Dmain.c19 COND_CODE_1(DT_NODE_HAS_PROP(node_id, memory_regions), \
20 (DT_REG_ADDR(DT_PHANDLE(node_id, memory_regions))), (0))
23 COND_CODE_1(DT_NODE_HAS_PROP(node_id, memory_regions), \
24 (DT_REG_SIZE(DT_PHANDLE(node_id, memory_regions))), (0))
/Zephyr-latest/scripts/coredump/coredump_parser/
Delf_parser.py59 self.memory_regions = list()
72 return self.memory_regions
141 self.memory_regions.append(mem_region)
Dlog_parser.py64 self.memory_regions = list()
77 return self.memory_regions
127 self.memory_regions.append(mem)
/Zephyr-latest/tests/boards/nrf/i2c/i2c_slave/src/
Dmain.c36 COND_CODE_1(DT_NODE_HAS_PROP(NODE_TWIS, memory_regions), \
38 LINKER_DT_NODE_REGION_NAME(DT_PHANDLE(NODE_TWIS, memory_regions)))))), \
/Zephyr-latest/drivers/pwm/
Dpwm_nrfx.c357 #define PWM_MEM_REGION(idx) DT_PHANDLE(PWM(idx), memory_regions)
360 COND_CODE_1(PWM_HAS_PROP(idx, memory_regions), \
366 COND_CODE_1(PWM_HAS_PROP(idx, memory_regions), \
/Zephyr-latest/drivers/i2c/
Di2c_nrfx_twim.c273 COND_CODE_1(I2C_HAS_PROP(idx, memory_regions), \
275 DT_PHANDLE(I2C(idx), memory_regions)))))), \
Di2c_nrfx_twim_rtio.c219 COND_CODE_1(I2C_HAS_PROP(idx, memory_regions), \
221 LINKER_DT_NODE_REGION_NAME(DT_PHANDLE(I2C(idx), memory_regions)))))), \
Di2c_nrfx_twis.c35 DT_NODE_HAS_PROP(id, memory_regions)
38 LINKER_DT_NODE_REGION_NAME(DT_PHANDLE(SHIM_NRF_TWIS_NODE(id), memory_regions))
/Zephyr-latest/tests/drivers/spi/spi_error_cases/src/
Dmain.c25 COND_CODE_1(DT_NODE_HAS_PROP(node, memory_regions), \
27 LINKER_DT_NODE_REGION_NAME(DT_PHANDLE(node, memory_regions)))))), \
/Zephyr-latest/drivers/adc/
Dadc_nrfx_saadc.c74 COND_CODE_1(DT_NODE_HAS_PROP(DT_NODELABEL(adc), memory_regions), \
76 DT_PHANDLE(DT_NODELABEL(adc), memory_regions)))))), \
/Zephyr-latest/drivers/spi/
Dspi_nrfx_spim.c751 #define SPIM_MEM_REGION(idx) DT_PHANDLE(SPIM(idx), memory_regions)
762 COND_CODE_1(SPIM_HAS_PROP(idx, memory_regions), \
854 COND_CODE_1(SPIM_HAS_PROP(idx, memory_regions), \
/Zephyr-latest/tests/drivers/spi/spi_controller_peripheral/src/
Dmain.c43 COND_CODE_1(DT_NODE_HAS_PROP(node, memory_regions), \
45 LINKER_DT_NODE_REGION_NAME(DT_PHANDLE(node, memory_regions)))))), \
/Zephyr-latest/drivers/serial/
Duart_nrfx_uarte2.c963 COND_CODE_1(UARTE_HAS_PROP(idx, memory_regions), \
965 DT_PHANDLE(UARTE(idx), memory_regions)))))), \
Duart_nrfx_uarte.c39 #define UARTE_IS_CACHEABLE(idx) DMM_IS_REG_CACHEABLE(DT_PHANDLE(UARTE(idx), memory_regions))