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Searched refs:dma_cfg (Results 1 – 25 of 60) sorted by relevance

123

/Zephyr-latest/tests/drivers/dma/chan_link_transfer/src/
Dtest_dma.c54 struct dma_config dma_cfg = { 0 }; in test_task() local
67 dma_cfg.channel_direction = MEMORY_TO_MEMORY; in test_task()
68 dma_cfg.source_data_size = 1U; in test_task()
69 dma_cfg.dest_data_size = 1U; in test_task()
70 dma_cfg.source_burst_length = 16; in test_task()
71 dma_cfg.dest_burst_length = 16; in test_task()
72 dma_cfg.dma_callback = test_done; in test_task()
73 dma_cfg.complete_callback_en = 0U; in test_task()
74 dma_cfg.error_callback_dis = 0U; in test_task()
75 dma_cfg.block_count = 1U; in test_task()
[all …]
/Zephyr-latest/tests/drivers/dma/loop_transfer/src/
Dtest_dma_loop.c41 static struct dma_config dma_cfg = {0}; variable
58 zassert_ok(dma_config(dev, id, &dma_cfg), "Not able to config transfer %d", in test_transfer()
107 dma_cfg.channel_direction = MEMORY_TO_MEMORY; in test_loop()
108 dma_cfg.source_data_size = 1U; in test_loop()
109 dma_cfg.dest_data_size = 1U; in test_loop()
110 dma_cfg.source_burst_length = 1U; in test_loop()
111 dma_cfg.dest_burst_length = 1U; in test_loop()
113 dma_cfg.user_data = (void *)dma; in test_loop()
115 dma_cfg.user_data = NULL; in test_loop()
117 dma_cfg.dma_callback = dma_user_callback; in test_loop()
[all …]
/Zephyr-latest/tests/boards/altera_max10/msgdma/src/
Ddma.c26 static struct dma_config dma_cfg = {0}; variable
56 dma_cfg.channel_direction = MEMORY_TO_MEMORY; in ZTEST()
57 dma_cfg.source_data_size = 1U; in ZTEST()
58 dma_cfg.dest_data_size = 1U; in ZTEST()
59 dma_cfg.source_burst_length = 1U; in ZTEST()
60 dma_cfg.dest_burst_length = 1U; in ZTEST()
61 dma_cfg.dma_callback = dma_user_callback; in ZTEST()
62 dma_cfg.block_count = 1U; in ZTEST()
63 dma_cfg.head_block = &dma_block_cfg; in ZTEST()
77 zassert_true(dma_config(dma, chan_id, &dma_cfg) == 0, in ZTEST()
/Zephyr-latest/drivers/dma/
Ddma_nxp_edma.c109 struct dma_config *dma_cfg) in edma_config() argument
120 if (!dma_cfg->head_block) { in edma_config()
126 if (!EDMA_TransferWidthIsValid(data->hal_cfg, dma_cfg->source_data_size)) { in edma_config()
128 dma_cfg->source_data_size); in edma_config()
133 if (!EDMA_TransferWidthIsValid(data->hal_cfg, dma_cfg->dest_data_size)) { in edma_config()
135 dma_cfg->dest_data_size); in edma_config()
147 if (dma_cfg->block_count != 1) { in edma_config()
148 LOG_ERR("number of blocks %d not supported", dma_cfg->block_count); in edma_config()
153 if (!dma_cfg->head_block->source_address) { in edma_config()
159 if (!dma_cfg->head_block->dest_address) { in edma_config()
[all …]
Ddma_rpi_pico.c114 struct dma_config *dma_cfg) in dma_rpi_pico_config() argument
124 if (dma_cfg->block_count != 1) { in dma_rpi_pico_config()
129 if (dma_cfg->channel_priority > 3) { in dma_rpi_pico_config()
130 LOG_ERR("channel_priority must be < 4 (%" PRIu32 ")", dma_cfg->channel_priority); in dma_rpi_pico_config()
134 if (dma_cfg->head_block->source_addr_adj == DMA_ADDR_ADJ_DECREMENT) { in dma_rpi_pico_config()
139 if (dma_cfg->head_block->dest_addr_adj == DMA_ADDR_ADJ_DECREMENT) { in dma_rpi_pico_config()
144 if (dma_cfg->head_block->source_addr_adj != DMA_ADDR_ADJ_INCREMENT && in dma_rpi_pico_config()
145 dma_cfg->head_block->source_addr_adj != DMA_ADDR_ADJ_NO_CHANGE) { in dma_rpi_pico_config()
146 LOG_ERR("invalid source_addr_adj %" PRIu16, dma_cfg->head_block->source_addr_adj); in dma_rpi_pico_config()
149 if (dma_cfg->head_block->dest_addr_adj != DMA_ADDR_ADJ_INCREMENT && in dma_rpi_pico_config()
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Ddma_gd32.c340 struct dma_config *dma_cfg) in dma_gd32_config() argument
355 if (dma_cfg->block_count != 1) { in dma_gd32_config()
360 if (dma_cfg->channel_priority > 3) { in dma_gd32_config()
362 dma_cfg->channel_priority); in dma_gd32_config()
366 if (dma_cfg->head_block->source_addr_adj == DMA_ADDR_ADJ_DECREMENT) { in dma_gd32_config()
371 if (dma_cfg->head_block->dest_addr_adj == DMA_ADDR_ADJ_DECREMENT) { in dma_gd32_config()
376 if (dma_cfg->head_block->source_addr_adj != DMA_ADDR_ADJ_INCREMENT && in dma_gd32_config()
377 dma_cfg->head_block->source_addr_adj != DMA_ADDR_ADJ_NO_CHANGE) { in dma_gd32_config()
379 dma_cfg->head_block->source_addr_adj); in dma_gd32_config()
382 if (dma_cfg->head_block->dest_addr_adj != DMA_ADDR_ADJ_INCREMENT && in dma_gd32_config()
[all …]
Ddma_intel_adsp_hda.c32 struct dma_config *dma_cfg) in intel_adsp_hda_dma_host_in_config() argument
40 __ASSERT(dma_cfg->block_count == 1, in intel_adsp_hda_dma_host_in_config()
43 __ASSERT(dma_cfg->channel_direction == cfg->direction, in intel_adsp_hda_dma_host_in_config()
47 blk_cfg = dma_cfg->head_block; in intel_adsp_hda_dma_host_in_config()
57 dma_cfg->source_data_size); in intel_adsp_hda_dma_host_in_config()
66 struct dma_config *dma_cfg) in intel_adsp_hda_dma_host_out_config() argument
74 __ASSERT(dma_cfg->block_count == 1, in intel_adsp_hda_dma_host_out_config()
77 __ASSERT(dma_cfg->channel_direction == cfg->direction, in intel_adsp_hda_dma_host_out_config()
81 blk_cfg = dma_cfg->head_block; in intel_adsp_hda_dma_host_out_config()
92 dma_cfg->dest_data_size); in intel_adsp_hda_dma_host_out_config()
[all …]
Ddma_intel_adsp_hda.h35 struct dma_config *dma_cfg);
39 struct dma_config *dma_cfg);
43 struct dma_config *dma_cfg);
47 struct dma_config *dma_cfg);
Ddma_nxp_edma.h477 static inline int set_slast_dlast(struct dma_config *dma_cfg, in set_slast_dlast() argument
487 switch (dma_cfg->head_block->source_addr_adj) { in set_slast_dlast()
489 slast = (int32_t)dma_cfg->head_block->block_size; in set_slast_dlast()
492 slast = (-1) * (int32_t)dma_cfg->head_block->block_size; in set_slast_dlast()
496 dma_cfg->head_block->source_addr_adj); in set_slast_dlast()
504 switch (dma_cfg->head_block->dest_addr_adj) { in set_slast_dlast()
506 dlast = (int32_t)dma_cfg->head_block->block_size; in set_slast_dlast()
509 dlast = (-1) * (int32_t)dma_cfg->head_block->block_size; in set_slast_dlast()
513 dma_cfg->head_block->dest_addr_adj); in set_slast_dlast()
/Zephyr-latest/tests/drivers/dma/scatter_gather/src/
Dtest_dma_sg.c39 static struct dma_config dma_cfg = {0}; variable
75 dma_cfg.channel_direction = MEMORY_TO_MEMORY; in test_sg()
76 dma_cfg.source_data_size = 4U; in test_sg()
77 dma_cfg.dest_data_size = 4U; in test_sg()
78 dma_cfg.source_burst_length = 4U; in test_sg()
79 dma_cfg.dest_burst_length = 4U; in test_sg()
81 dma_cfg.user_data = (struct device *)dma; in test_sg()
83 dma_cfg.user_data = NULL; in test_sg()
85 dma_cfg.dma_callback = dma_sg_callback; in test_sg()
86 dma_cfg.block_count = XFERS; in test_sg()
[all …]
/Zephyr-latest/tests/drivers/dma/chan_blen_transfer/src/
Dtest_dma.c37 struct dma_config dma_cfg = { 0 }; in test_task() local
45 dma_cfg.channel_direction = MEMORY_TO_MEMORY; in test_task()
46 dma_cfg.source_data_size = 1U; in test_task()
47 dma_cfg.dest_data_size = 1U; in test_task()
48 dma_cfg.source_burst_length = blen; in test_task()
49 dma_cfg.dest_burst_length = blen; in test_task()
50 dma_cfg.dma_callback = test_done; in test_task()
51 dma_cfg.complete_callback_en = 0U; in test_task()
52 dma_cfg.error_callback_dis = 0U; in test_task()
53 dma_cfg.block_count = 1U; in test_task()
[all …]
/Zephyr-latest/tests/boards/intel_adsp/ssp/src/
Dmain.c60 static struct dma_config dma_cfg = {0}; variable
106 dma_cfg.dma_slot = props->dma_hs_id; in config_output_dma()
107 dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL; in config_output_dma()
108 dma_cfg.dest_handshake = 0; in config_output_dma()
109 dma_cfg.source_handshake = 0; in config_output_dma()
110 dma_cfg.cyclic = 1; in config_output_dma()
111 dma_cfg.source_data_size = 1; in config_output_dma()
112 dma_cfg.dest_data_size = 1; in config_output_dma()
113 dma_cfg.source_burst_length = 1; in config_output_dma()
114 dma_cfg.dest_burst_length = 1; in config_output_dma()
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/Zephyr-latest/drivers/display/
Ddisplay_renesas_lcdc.c71 struct dma_config dma_cfg; member
233 data->dma_cfg.channel_direction = MEMORY_TO_MEMORY; in display_smartbond_dma_config()
234 data->dma_cfg.user_data = data; in display_smartbond_dma_config()
235 data->dma_cfg.dma_callback = display_smartbond_dma_cb; in display_smartbond_dma_config()
236 data->dma_cfg.block_count = 1; in display_smartbond_dma_config()
237 data->dma_cfg.head_block = &data->dma_block_cfg; in display_smartbond_dma_config()
238 data->dma_cfg.error_callback_dis = 1; in display_smartbond_dma_config()
483 data->dma_cfg.source_data_size = data->dma_cfg.dest_data_size = in display_smartbond_read()
487 data->dma_cfg.dest_burst_length = data->dma_cfg.source_burst_length = in display_smartbond_read()
488 !((data->dma_block_cfg.block_size / data->dma_cfg.source_data_size) & 7) ? 8 : in display_smartbond_read()
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/Zephyr-latest/drivers/usb/udc/
Dudc_smartbond.c60 struct usb_smartbond_dma_config dma_cfg; member
129 const struct usb_smartbond_dma_config *dma_cfg = &config->dma_cfg; in usb_smartbond_dma_config() local
135 if (dma_request_channel(dma_cfg->rx_dev, (void *)&dma_cfg->rx_chan) < 0) { in usb_smartbond_dma_config()
140 if (dma_request_channel(dma_cfg->tx_dev, (void *)&dma_cfg->tx_chan) < 0) { in usb_smartbond_dma_config()
155 tx->dma_slot = dma_cfg->tx_slot_mux; in usb_smartbond_dma_config()
187 rx->dma_slot = dma_cfg->rx_slot_mux; in usb_smartbond_dma_config()
209 if (dma_config(dma_cfg->rx_dev, dma_cfg->rx_chan, rx) < 0) { in usb_smartbond_dma_config()
214 if (dma_config(dma_cfg->tx_dev, dma_cfg->tx_chan, tx) < 0) { in usb_smartbond_dma_config()
225 const struct usb_smartbond_dma_config *dma_cfg = &config->dma_cfg; in usb_smartbond_dma_deconfig() local
227 dma_stop(dma_cfg->tx_dev, dma_cfg->tx_chan); in usb_smartbond_dma_deconfig()
[all …]
/Zephyr-latest/drivers/i2c/
Di2c_sam0.c280 struct dma_config dma_cfg = { 0 }; in i2c_sam0_dma_write_start() local
283 dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL; in i2c_sam0_dma_write_start()
284 dma_cfg.source_data_size = 1; in i2c_sam0_dma_write_start()
285 dma_cfg.dest_data_size = 1; in i2c_sam0_dma_write_start()
286 dma_cfg.user_data = (void *)dev; in i2c_sam0_dma_write_start()
287 dma_cfg.dma_callback = i2c_sam0_dma_write_done; in i2c_sam0_dma_write_start()
288 dma_cfg.block_count = 1; in i2c_sam0_dma_write_start()
289 dma_cfg.head_block = &dma_blk; in i2c_sam0_dma_write_start()
290 dma_cfg.dma_slot = cfg->write_dma_request; in i2c_sam0_dma_write_start()
297 retval = dma_config(cfg->dma_dev, cfg->dma_channel, &dma_cfg); in i2c_sam0_dma_write_start()
[all …]
Di2c_dw.c109 struct dma_config dma_cfg = {0}; in i2c_dw_idma_rx_transfer() local
117 dma_cfg.dma_slot = 1U; in i2c_dw_idma_rx_transfer()
118 dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY; in i2c_dw_idma_rx_transfer()
119 dma_cfg.source_data_size = 1U; in i2c_dw_idma_rx_transfer()
120 dma_cfg.dest_data_size = 1U; in i2c_dw_idma_rx_transfer()
121 dma_cfg.source_burst_length = 1U; in i2c_dw_idma_rx_transfer()
122 dma_cfg.dest_burst_length = 1U; in i2c_dw_idma_rx_transfer()
123 dma_cfg.dma_callback = cb_i2c_idma_transfer; in i2c_dw_idma_rx_transfer()
124 dma_cfg.user_data = (void *)dev; in i2c_dw_idma_rx_transfer()
125 dma_cfg.complete_callback_en = 0U; in i2c_dw_idma_rx_transfer()
[all …]
Di2c_max32.c309 struct dma_config dma_cfg = {0}; in i2c_max32_tx_dma_load() local
312 dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL; in i2c_max32_tx_dma_load()
313 dma_cfg.dma_callback = i2c_max32_dma_callback; in i2c_max32_tx_dma_load()
314 dma_cfg.user_data = (void *)data; in i2c_max32_tx_dma_load()
315 dma_cfg.dma_slot = config->tx_dma.slot; in i2c_max32_tx_dma_load()
316 dma_cfg.block_count = 1; in i2c_max32_tx_dma_load()
317 dma_cfg.source_data_size = 1U; in i2c_max32_tx_dma_load()
318 dma_cfg.source_burst_length = 1U; in i2c_max32_tx_dma_load()
319 dma_cfg.dest_data_size = 1U; in i2c_max32_tx_dma_load()
320 dma_cfg.head_block = &dma_blk; in i2c_max32_tx_dma_load()
[all …]
/Zephyr-latest/drivers/i2s/
Di2s_mcux_flexcomm.c38 struct dma_config dma_cfg; member
304 stream->dma_cfg.dest_data_size = 4U; in i2s_mcux_configure()
305 stream->dma_cfg.source_data_size = 4U; in i2s_mcux_configure()
424 stream->dma_cfg.head_block = blk_cfg; in i2s_mcux_config_dma_blocks()
444 stream->dma_cfg.user_data = (void *)dev; in i2s_mcux_config_dma_blocks()
446 dma_config(stream->dev_dma, stream->channel, &stream->dma_cfg); in i2s_mcux_config_dma_blocks()
448 LOG_DBG("dma_slot is %d", stream->dma_cfg.dma_slot); in i2s_mcux_config_dma_blocks()
449 LOG_DBG("channel_direction is %d", stream->dma_cfg.channel_direction); in i2s_mcux_config_dma_blocks()
451 stream->dma_cfg.complete_callback_en); in i2s_mcux_config_dma_blocks()
452 LOG_DBG("error_callback_dis is %d", stream->dma_cfg.error_callback_dis); in i2s_mcux_config_dma_blocks()
[all …]
/Zephyr-latest/drivers/adc/
Dadc_mcux_adc16.c54 struct dma_config dma_cfg; member
285 data->adc_dma_config.dma_cfg.head_block = in adc_context_start_sampling()
288 &data->adc_dma_config.dma_cfg); in adc_context_start_sampling()
391 data->adc_dma_config.dma_cfg.block_count = 1U; in mcux_adc16_init()
392 data->adc_dma_config.dma_cfg.dma_slot = config->dma_slot; in mcux_adc16_init()
393 data->adc_dma_config.dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY; in mcux_adc16_init()
394 data->adc_dma_config.dma_cfg.source_burst_length = 2U; in mcux_adc16_init()
395 data->adc_dma_config.dma_cfg.dest_burst_length = 2U; in mcux_adc16_init()
396 data->adc_dma_config.dma_cfg.channel_priority = 0U; in mcux_adc16_init()
397 data->adc_dma_config.dma_cfg.dma_callback = adc_dma_callback; in mcux_adc16_init()
[all …]
/Zephyr-latest/drivers/spi/
Dspi_andes_atcspi200.c27 struct dma_config dma_cfg; member
313 data->dma_tx.dma_cfg.dest_data_size; in spi_dma_tx_load()
316 data->dma_tx.dma_cfg.dest_data_size; in spi_dma_tx_load()
347 data->dma_tx.dma_cfg.head_block = &data->dma_tx.dma_blk_cfg; in spi_dma_tx_load()
348 data->dma_tx.dma_cfg.head_block->next_block = NULL; in spi_dma_tx_load()
350 data->dma_tx.dma_cfg.user_data = (void *)dev; in spi_dma_tx_load()
352 if (data->dma_tx.dma_cfg.source_chaining_en) { in spi_dma_tx_load()
353 data->dma_tx.dma_cfg.block_count = ctx->tx_count; in spi_dma_tx_load()
354 data->dma_tx.dma_cfg.dma_callback = NULL; in spi_dma_tx_load()
369 data->dma_tx.dma_cfg.dest_data_size; in spi_dma_tx_load()
[all …]
Dspi_sam0.c412 struct dma_config dma_cfg = { 0 }; in spi_sam0_dma_rx_load() local
416 dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY; in spi_sam0_dma_rx_load()
417 dma_cfg.source_data_size = 1; in spi_sam0_dma_rx_load()
418 dma_cfg.dest_data_size = 1; in spi_sam0_dma_rx_load()
419 dma_cfg.user_data = data; in spi_sam0_dma_rx_load()
420 dma_cfg.dma_callback = spi_sam0_dma_rx_done; in spi_sam0_dma_rx_load()
421 dma_cfg.block_count = 1; in spi_sam0_dma_rx_load()
422 dma_cfg.head_block = &dma_blk; in spi_sam0_dma_rx_load()
423 dma_cfg.dma_slot = cfg->rx_dma_request; in spi_sam0_dma_rx_load()
440 &dma_cfg); in spi_sam0_dma_rx_load()
[all …]
Dspi_gd32.c254 struct dma_config *dma_cfg = &data->dma[dir].config; in spi_gd32_dma_setup() local
259 memset(dma_cfg, 0, sizeof(struct dma_config)); in spi_gd32_dma_setup()
262 dma_cfg->source_burst_length = 1; in spi_gd32_dma_setup()
263 dma_cfg->dest_burst_length = 1; in spi_gd32_dma_setup()
264 dma_cfg->user_data = (void *)dev; in spi_gd32_dma_setup()
265 dma_cfg->dma_callback = spi_gd32_dma_callback; in spi_gd32_dma_setup()
266 dma_cfg->block_count = 1U; in spi_gd32_dma_setup()
267 dma_cfg->head_block = block_cfg; in spi_gd32_dma_setup()
268 dma_cfg->dma_slot = cfg->dma[dir].slot; in spi_gd32_dma_setup()
269 dma_cfg->channel_priority = in spi_gd32_dma_setup()
[all …]
Dspi_mcux_dspi.c35 struct dma_config dma_cfg; member
381 data->tx_dma_config.dma_cfg.user_data = (void *) dev; in update_tx_dma()
383 (struct dma_config *)&data->tx_dma_config.dma_cfg); in update_tx_dma()
423 data->rx_dma_config.dma_cfg.source_chaining_en = 0; in update_rx_dma()
424 data->rx_dma_config.dma_cfg.dest_chaining_en = 0; in update_rx_dma()
427 data->rx_dma_config.dma_cfg.source_chaining_en = 1; in update_rx_dma()
428 data->rx_dma_config.dma_cfg.dest_chaining_en = 1; in update_rx_dma()
429 data->rx_dma_config.dma_cfg.linked_channel = in update_rx_dma()
438 data->rx_dma_config.dma_cfg.source_burst_length = in update_rx_dma()
440 data->rx_dma_config.dma_cfg.dest_burst_length = frame_size_byte; in update_rx_dma()
[all …]
Dspi_max32.c462 struct dma_config dma_cfg = {0}; in spi_max32_tx_dma_load() local
465 dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL; in spi_max32_tx_dma_load()
466 dma_cfg.dma_callback = spi_max32_dma_callback; in spi_max32_tx_dma_load()
467 dma_cfg.user_data = (void *)data; in spi_max32_tx_dma_load()
468 dma_cfg.dma_slot = config->tx_dma.slot; in spi_max32_tx_dma_load()
469 dma_cfg.block_count = 1; in spi_max32_tx_dma_load()
470 dma_cfg.source_data_size = 1U << word_shift; in spi_max32_tx_dma_load()
471 dma_cfg.source_burst_length = 1U; in spi_max32_tx_dma_load()
472 dma_cfg.dest_data_size = 1U << word_shift; in spi_max32_tx_dma_load()
473 dma_cfg.head_block = &dma_blk; in spi_max32_tx_dma_load()
[all …]
/Zephyr-latest/drivers/video/
Dvideo_esp32_dvp.c141 struct dma_config dma_cfg = {0}; in video_esp32_stream_start() local
178 dma_cfg.block_count = i + 1; in video_esp32_stream_start()
193 dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY; in video_esp32_stream_start()
194 dma_cfg.dma_callback = video_esp32_dma_rx_done; in video_esp32_stream_start()
195 dma_cfg.user_data = data; in video_esp32_stream_start()
196 dma_cfg.dma_slot = SOC_GDMA_TRIG_PERIPH_CAM0; in video_esp32_stream_start()
197 dma_cfg.complete_callback_en = 1; in video_esp32_stream_start()
198 dma_cfg.head_block = &data->dma_blocks[0]; in video_esp32_stream_start()
200 error = dma_config(cfg->dma_dev, cfg->rx_dma_channel, &dma_cfg); in video_esp32_stream_start()

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