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Searched refs:dev_cfg (Results 1 – 25 of 72) sorted by relevance

123

/Zephyr-latest/drivers/mdio/
Dmdio_gpio.c31 static ALWAYS_INLINE void mdio_gpio_clock_the_bit(const struct mdio_gpio_config *dev_cfg) in mdio_gpio_clock_the_bit() argument
34 gpio_pin_set_dt(&dev_cfg->mdc_gpio, 1); in mdio_gpio_clock_the_bit()
36 gpio_pin_set_dt(&dev_cfg->mdc_gpio, 0); in mdio_gpio_clock_the_bit()
39 static ALWAYS_INLINE void mdio_gpio_dir(const struct mdio_gpio_config *dev_cfg, uint8_t dir) in mdio_gpio_dir() argument
41 gpio_pin_configure_dt(&dev_cfg->mdio_gpio, dir ? GPIO_OUTPUT_ACTIVE : GPIO_INPUT); in mdio_gpio_dir()
43 mdio_gpio_clock_the_bit(dev_cfg); in mdio_gpio_dir()
47 static ALWAYS_INLINE void mdio_gpio_read(const struct mdio_gpio_config *dev_cfg, uint16_t *pdata) in mdio_gpio_read() argument
53 mdio_gpio_clock_the_bit(dev_cfg); in mdio_gpio_read()
54 if (gpio_pin_get_dt(&dev_cfg->mdio_gpio) == 1) { in mdio_gpio_read()
62 static ALWAYS_INLINE void mdio_gpio_write(const struct mdio_gpio_config *dev_cfg, in mdio_gpio_write() argument
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Dmdio_litex_liteeth.c38 static void mdio_litex_read(const struct mdio_litex_config *dev_cfg, uint16_t *pdata) in mdio_litex_read() argument
44 if (litex_read8(dev_cfg->r_addr) & LITEX_MDIO_DI) { in mdio_litex_read()
47 litex_write8(LITEX_MDIO_CLK, dev_cfg->w_addr); in mdio_litex_read()
49 litex_write8(0, dev_cfg->w_addr); in mdio_litex_read()
58 static void mdio_litex_write(const struct mdio_litex_config *dev_cfg, uint32_t data, uint8_t len) in mdio_litex_write() argument
68 litex_write8(LITEX_MDIO_DO | LITEX_MDIO_OE, dev_cfg->w_addr); in mdio_litex_write()
71 dev_cfg->w_addr); in mdio_litex_write()
73 litex_write8(LITEX_MDIO_DO | LITEX_MDIO_OE, dev_cfg->w_addr); in mdio_litex_write()
75 litex_write8(LITEX_MDIO_OE, dev_cfg->w_addr); in mdio_litex_write()
77 litex_write8(LITEX_MDIO_CLK | LITEX_MDIO_OE, dev_cfg->w_addr); in mdio_litex_write()
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/Zephyr-latest/drivers/sensor/st/qdec_stm32/
Dqdec_stm32.c47 const struct qdec_stm32_dev_cfg *dev_cfg = dev->config; in qdec_stm32_fetch() local
58 counter_value = LL_TIM_GetCounter(dev_cfg->timer_inst) % dev_cfg->counts_per_revolution; in qdec_stm32_fetch()
59 dev_data->position = (counter_value * 360) / dev_cfg->counts_per_revolution; in qdec_stm32_fetch()
81 const struct qdec_stm32_dev_cfg *const dev_cfg = dev->config; in qdec_stm32_initialize() local
86 retval = pinctrl_apply_state(dev_cfg->pin_config, PINCTRL_STATE_DEFAULT); in qdec_stm32_initialize()
97 (clock_control_subsys_t)&dev_cfg->pclken); in qdec_stm32_initialize()
103 if (dev_cfg->counts_per_revolution < 1) { in qdec_stm32_initialize()
105 dev_cfg->counts_per_revolution); in qdec_stm32_initialize()
111 init_props.EncoderMode = dev_cfg->encoder_mode; in qdec_stm32_initialize()
113 if (dev_cfg->is_input_polarity_inverted) { in qdec_stm32_initialize()
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/Zephyr-latest/drivers/spi/
Dspi_numaker.c59 const struct spi_numaker_config *dev_cfg = dev->config; in spi_numaker_configure() local
77 SPI_ClearRxFIFO(dev_cfg->spi); in spi_numaker_configure()
78 SPI_ClearTxFIFO(dev_cfg->spi); in spi_numaker_configure()
87 if (dev_cfg->is_qspi) { in spi_numaker_configure()
88 QSPI_Open((QSPI_T *)dev_cfg->spi, in spi_numaker_configure()
94 SPI_Open(dev_cfg->spi, in spi_numaker_configure()
103 SPI_SET_LSB_FIRST(dev_cfg->spi); in spi_numaker_configure()
105 SPI_SET_MSB_FIRST(dev_cfg->spi); in spi_numaker_configure()
111 SPI_ENABLE_3WIRE_MODE(dev_cfg->spi); in spi_numaker_configure()
114 SPI_DISABLE_3WIRE_MODE(dev_cfg->spi); in spi_numaker_configure()
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/Zephyr-latest/drivers/counter/
Dcounter_sam_tc.c101 const struct counter_sam_dev_cfg *const dev_cfg = dev->config; in counter_sam_tc_start() local
102 Tc *tc = dev_cfg->regs; in counter_sam_tc_start()
103 TcChannel *tc_ch = &tc->TcChannel[dev_cfg->tc_chan_num]; in counter_sam_tc_start()
112 const struct counter_sam_dev_cfg *const dev_cfg = dev->config; in counter_sam_tc_stop() local
113 Tc *tc = dev_cfg->regs; in counter_sam_tc_stop()
114 TcChannel *tc_ch = &tc->TcChannel[dev_cfg->tc_chan_num]; in counter_sam_tc_stop()
123 const struct counter_sam_dev_cfg *const dev_cfg = dev->config; in counter_sam_tc_get_value() local
124 Tc *tc = dev_cfg->regs; in counter_sam_tc_get_value()
125 TcChannel *tc_ch = &tc->TcChannel[dev_cfg->tc_chan_num]; in counter_sam_tc_get_value()
136 const struct counter_sam_dev_cfg *const dev_cfg = dev->config; in counter_sam_tc_set_alarm() local
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/Zephyr-latest/drivers/sensor/tdk/icm42688/
Dicm42688_common.c24 const struct icm42688_dev_cfg *dev_cfg = dev->config; in icm42688_reset() local
30 res = icm42688_spi_single_write(&dev_cfg->spi, REG_DEVICE_CONFIG, BIT_SOFT_RESET); in icm42688_reset()
41 res = icm42688_spi_read(&dev_cfg->spi, REG_INT_STATUS, &value, 1); in icm42688_reset()
52 res = icm42688_spi_read(&dev_cfg->spi, REG_WHO_AM_I, &value, 1); in icm42688_reset()
124 const struct icm42688_dev_cfg *dev_cfg = dev->config; in icm42688_configure() local
128 res = icm42688_spi_single_write(&dev_cfg->spi, REG_INT_SOURCE0, 0); in icm42688_configure()
132 res = icm42688_spi_single_write(&dev_cfg->spi, REG_FIFO_CONFIG, in icm42688_configure()
140 res = icm42688_spi_single_write(&dev_cfg->spi, REG_SIGNAL_PATH_RESET, in icm42688_configure()
157 res = icm42688_spi_single_write(&dev_cfg->spi, REG_PWR_MGMT0, pwr_mgmt0); in icm42688_configure()
173 res = icm42688_spi_single_write(&dev_cfg->spi, REG_ACCEL_CONFIG0, accel_config0); in icm42688_configure()
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/Zephyr-latest/drivers/watchdog/
Dwdt_ambiq.c53 const struct wdt_ambiq_config *dev_cfg = dev->config; in wdt_ambiq_setup() local
60 if (dev_cfg->clk_freq == 128) { in wdt_ambiq_setup()
62 } else if (dev_cfg->clk_freq == 16) { in wdt_ambiq_setup()
64 } else if (dev_cfg->clk_freq == 1) { in wdt_ambiq_setup()
76 if (dev_cfg->clk_freq == 128) { in wdt_ambiq_setup()
78 } else if (dev_cfg->clk_freq == 16) { in wdt_ambiq_setup()
80 } else if (dev_cfg->clk_freq == 1) { in wdt_ambiq_setup()
111 const struct wdt_ambiq_config *dev_cfg = dev->config; in wdt_ambiq_install_timeout() local
118 data->timeout = cfg->window.max / 1000 * dev_cfg->clk_freq; in wdt_ambiq_install_timeout()
154 const struct wdt_ambiq_config *dev_cfg = dev->config; in wdt_ambiq_init() local
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/Zephyr-latest/drivers/mspi/
Dmspi_emul.c53 struct mspi_dev_cfg dev_cfg; member
189 data->dev_cfg.cmd_length = xfer->cmd_length; in mspi_xfer_config()
190 data->dev_cfg.addr_length = xfer->addr_length; in mspi_xfer_config()
191 data->dev_cfg.tx_dummy = xfer->tx_dummy; in mspi_xfer_config()
192 data->dev_cfg.rx_dummy = xfer->rx_dummy; in mspi_xfer_config()
208 const struct mspi_dev_cfg *dev_cfg) in mspi_dev_cfg_check_save() argument
213 data->dev_cfg.ce_num = dev_cfg->ce_num; in mspi_dev_cfg_check_save()
217 if (dev_cfg->freq > MSPI_MAX_FREQ) { in mspi_dev_cfg_check_save()
221 data->dev_cfg.freq = dev_cfg->freq; in mspi_dev_cfg_check_save()
225 if (dev_cfg->io_mode >= MSPI_IO_MODE_MAX) { in mspi_dev_cfg_check_save()
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/Zephyr-latest/drivers/serial/
Duart_mchp_xec.c242 struct uart_xec_device_config const *dev_cfg = dev->config; in uart_clr_slp_en() local
244 z_mchp_xec_pcr_periph_sleep(dev_cfg->pcr_idx, dev_cfg->pcr_bitpos, 0); in uart_clr_slp_en()
249 struct uart_xec_device_config const *dev_cfg = dev->config; in uart_xec_girq_clr() local
251 mchp_soc_ecia_girq_src_clr(dev_cfg->girq_id, dev_cfg->girq_pos); in uart_xec_girq_clr()
263 struct uart_xec_device_config const *dev_cfg = dev->config; in uart_clr_slp_en() local
265 if (dev_cfg->pcr_bitpos == MCHP_PCR2_UART0_POS) { in uart_clr_slp_en()
267 } else if (dev_cfg->pcr_bitpos == MCHP_PCR2_UART1_POS) { in uart_clr_slp_en()
276 struct uart_xec_device_config const *dev_cfg = dev->config; in uart_xec_girq_clr() local
278 MCHP_GIRQ_SRC(dev_cfg->girq_id) = BIT(dev_cfg->girq_pos); in uart_xec_girq_clr()
290 const struct uart_xec_device_config * const dev_cfg = dev->config; in set_baud_rate() local
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Duart_cmsdk_apb.c101 const struct uart_cmsdk_apb_config * const dev_cfg = dev->config; in baudrate_set() local
108 if ((dev_data->baud_rate != 0U) && (dev_cfg->sys_clk_freq != 0U)) { in baudrate_set()
110 dev_cfg->uart->bauddiv = (dev_cfg->sys_clk_freq / dev_data->baud_rate); in baudrate_set()
126 const struct uart_cmsdk_apb_config * const dev_cfg = dev->config; in uart_cmsdk_apb_init() local
148 dev_cfg->uart->ctrl = UART_RX_EN | UART_TX_EN; in uart_cmsdk_apb_init()
151 dev_cfg->irq_config_func(dev); in uart_cmsdk_apb_init()
168 const struct uart_cmsdk_apb_config *dev_cfg = dev->config; in uart_cmsdk_apb_poll_in() local
171 if (!(dev_cfg->uart->state & UART_RX_BF)) { in uart_cmsdk_apb_poll_in()
176 *c = (unsigned char)dev_cfg->uart->data; in uart_cmsdk_apb_poll_in()
193 const struct uart_cmsdk_apb_config *dev_cfg = dev->config; in uart_cmsdk_apb_poll_out() local
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Duart_ns16550.c504 const struct uart_ns16550_dev_config * const dev_cfg = dev->config; local
520 ns16550_outbyte(dev_cfg, ECSPMR(dev), ECSPMR_ECHS);
524 ns16550_outbyte(dev_cfg, ECSPMR(dev), 0);
533 const struct uart_ns16550_dev_config * const dev_cfg = dev->config; local
535 if ((ns16550_inbyte(dev_cfg, LSR(dev)) & LSR_RXRDY) != 0) {
536 *c = ns16550_inbyte(dev_cfg, RDR(dev));
546 const struct uart_ns16550_dev_config * const dev_cfg = dev->config; local
557 lcr_cache = ns16550_inbyte(dev_cfg, LCR(dev));
558 ns16550_outbyte(dev_cfg, LCR(dev), LCR_DLAB | lcr_cache);
559 ns16550_outbyte(dev_cfg, BRDL(dev), (unsigned char)(divisor & 0xff));
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/Zephyr-latest/drivers/input/
Dinput_ili2132a.c44 const struct ili2132a_config *dev_cfg = dev->config; in ili2132a_process() local
49 ret = i2c_read_dt(&dev_cfg->i2c, buf, sizeof(buf)); in ili2132a_process()
76 const struct ili2132a_config *dev_cfg = dev->config; in ili2132a_init() local
79 if (!i2c_is_ready_dt(&dev_cfg->i2c)) { in ili2132a_init()
80 LOG_ERR("%s is not ready", dev_cfg->i2c.bus->name); in ili2132a_init()
84 if (!gpio_is_ready_dt(&dev_cfg->rst)) { in ili2132a_init()
89 if (!gpio_is_ready_dt(&dev_cfg->irq)) { in ili2132a_init()
96 ret = gpio_pin_configure_dt(&dev_cfg->irq, GPIO_INPUT); in ili2132a_init()
102 ret = gpio_pin_configure_dt(&dev_cfg->rst, GPIO_OUTPUT_ACTIVE); in ili2132a_init()
108 ret = gpio_pin_set_dt(&dev_cfg->rst, 0); in ili2132a_init()
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Dinput_esp32_touch_sensor.c80 const struct esp32_touch_sensor_config *dev_cfg = dev->config; local
82 const int num_channels = dev_cfg->num_channels;
97 channel_cfg = &dev_cfg->channel_cfg[i];
119 channel_cfg = &dev_cfg->channel_cfg[i];
130 *channel_data = &dev_cfg->channel_data[i];
134 K_MSEC(dev_cfg->debounce_interval_ms));
161 const struct esp32_touch_sensor_config *dev_cfg = dev->config; local
162 int key_index = channel_data - &dev_cfg->channel_data[0];
164 *channel_cfg = &dev_cfg->channel_cfg[key_index];
181 const struct esp32_touch_sensor_config *dev_cfg = dev->config; local
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/Zephyr-latest/drivers/dma/
Ddma_dw_common.c29 const struct dw_dma_dev_cfg *const dev_cfg = dev->config; in dw_dma_isr() local
39 status_intr = dw_read(dev_cfg->base, DW_INTR_STATUS); in dw_dma_isr()
45 status_block = dw_read(dev_cfg->base, DW_STATUS_BLOCK); in dw_dma_isr()
46 status_tfr = dw_read(dev_cfg->base, DW_STATUS_TFR); in dw_dma_isr()
49 status_err = dw_read(dev_cfg->base, DW_STATUS_ERR); in dw_dma_isr()
52 dw_write(dev_cfg->base, DW_CLEAR_ERR, status_err); in dw_dma_isr()
56 dw_write(dev_cfg->base, DW_CLEAR_BLOCK, status_block); in dw_dma_isr()
57 dw_write(dev_cfg->base, DW_CLEAR_TFR, status_tfr); in dw_dma_isr()
127 const struct dw_dma_dev_cfg *const dev_cfg = dev->config; in dw_dma_config() local
416 dw_write(dev_cfg->base, DW_MASK_BLOCK, DW_CHAN_UNMASK(channel)); in dw_dma_config()
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Ddma_intel_adsp_gpdma.c58 const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config; in intel_adsp_gpdma_dump_registers() local
59 const struct dw_dma_dev_cfg *const dw_cfg = &dev_cfg->dw_cfg; in intel_adsp_gpdma_dump_registers()
64 cap = dw_read(dev_cfg->shim, 0x0); in intel_adsp_gpdma_dump_registers()
65 ctl = dw_read(dev_cfg->shim, 0x4); in intel_adsp_gpdma_dump_registers()
66 ipptr = dw_read(dev_cfg->shim, 0x8); in intel_adsp_gpdma_dump_registers()
67 llpc = dw_read(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel)); in intel_adsp_gpdma_dump_registers()
68 llpl = dw_read(dev_cfg->shim, GPDMA_CHLLPL(channel)); in intel_adsp_gpdma_dump_registers()
69 llpu = dw_read(dev_cfg->shim, GPDMA_CHLLPU(channel)); in intel_adsp_gpdma_dump_registers()
93 const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config; in intel_adsp_gpdma_llp_config() local
95 dw_write(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel), in intel_adsp_gpdma_llp_config()
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Ddma_intel_lpss.c31 struct dma_intel_lpss_cfg *dev_cfg = (struct dma_intel_lpss_cfg *)dev->config; in dma_intel_lpss_setup() local
33 if (dev_cfg->dw_cfg.base != 0) { in dma_intel_lpss_setup()
42 struct dma_intel_lpss_cfg *dev_cfg = (struct dma_intel_lpss_cfg *)dev->config; in dma_intel_lpss_set_base() local
44 dev_cfg->dw_cfg.base = base; in dma_intel_lpss_set_base()
57 struct dw_dma_dev_cfg *const dev_cfg = &lpss_dev_cfg->dw_cfg; in dma_intel_lpss_reload() local
72 ctrl_hi = dw_read(dev_cfg->base, DW_CTRL_HIGH(channel)); in dma_intel_lpss_reload()
92 struct dw_dma_dev_cfg *const dev_cfg = &lpss_dev_cfg->dw_cfg; in dma_intel_lpss_get_status() local
104 ctrl_hi = dw_read(dev_cfg->base, DW_CTRL_HIGH(channel)); in dma_intel_lpss_get_status()
108 if (!(dw_read(dev_cfg->base, DW_DMA_CHAN_EN) & DW_CHAN(channel))) { in dma_intel_lpss_get_status()
/Zephyr-latest/drivers/gpio/
Dgpio_ambiq.c38 const struct ambiq_gpio_config *const dev_cfg = dev->config; in ambiq_gpio_pin_configure() local
42 pin += dev_cfg->offset; in ambiq_gpio_pin_configure()
81 pin += (dev_cfg->offset >> 2); in ambiq_gpio_pin_configure()
131 const struct ambiq_gpio_config *const dev_cfg = dev->config; in ambiq_gpio_get_config() local
135 pin += dev_cfg->offset; in ambiq_gpio_get_config()
168 pin += (dev_cfg->offset >> 2); in ambiq_gpio_get_config()
209 const struct ambiq_gpio_config *const dev_cfg = dev->config; in ambiq_gpio_port_get_direction() local
214 uint32_t pin_offset = dev_cfg->offset; in ambiq_gpio_port_get_direction()
217 for (int i = 0; i < dev_cfg->ngpios; i++) { in ambiq_gpio_port_get_direction()
228 for (int i = 0; i < dev_cfg->ngpios; i++) { in ambiq_gpio_port_get_direction()
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/Zephyr-latest/drivers/ethernet/
Deth_xmc4xxx.c139 const struct eth_xmc4xxx_config *dev_cfg = dev->config; in eth_xmc4xxx_tx_dma_descriptors_init() local
143 dev_cfg->regs->TRANSMIT_DESCRIPTOR_LIST_ADDRESS = (uint32_t)&tx_dma_desc[0]; in eth_xmc4xxx_tx_dma_descriptors_init()
159 const struct eth_xmc4xxx_config *dev_cfg = dev->config; in eth_xmc4xxx_flush_rx() local
162 dev_cfg->regs->OPERATION_MODE &= ~ETH_OPERATION_MODE_SR_Msk; in eth_xmc4xxx_flush_rx()
168 dev_cfg->regs->OPERATION_MODE |= ETH_OPERATION_MODE_SR_Msk; in eth_xmc4xxx_flush_rx()
174 const struct eth_xmc4xxx_config *dev_cfg = dev->config; in eth_xmc4xxx_flush_tx() local
184 dev_cfg->regs->OPERATION_MODE &= ~ETH_OPERATION_MODE_ST_Msk; in eth_xmc4xxx_flush_tx()
203 dev_cfg->regs->OPERATION_MODE |= ETH_OPERATION_MODE_ST_Msk; in eth_xmc4xxx_flush_tx()
227 const struct eth_xmc4xxx_config *dev_cfg = dev->config; in eth_xmc4xxx_send() local
253 eth_xmc4xxx_trigger_dma_tx(dev_cfg->regs); in eth_xmc4xxx_send()
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/Zephyr-latest/drivers/dac/
Ddac_sam.c55 const struct dac_sam_dev_cfg *const dev_cfg = dev->config; in dac_sam_isr() local
57 Dacc *const dac = dev_cfg->regs; in dac_sam_isr()
78 const struct dac_sam_dev_cfg *const dev_cfg = dev->config; in dac_sam_channel_setup() local
79 Dacc *const dac = dev_cfg->regs; in dac_sam_channel_setup()
102 const struct dac_sam_dev_cfg *const dev_cfg = dev->config; in dac_sam_write_value() local
103 Dacc *const dac = dev_cfg->regs; in dac_sam_write_value()
132 const struct dac_sam_dev_cfg *const dev_cfg = dev->config; in dac_sam_init() local
134 Dacc *const dac = dev_cfg->regs; in dac_sam_init()
138 dev_cfg->irq_config(); in dac_sam_init()
147 (clock_control_subsys_t)&dev_cfg->clock_cfg); in dac_sam_init()
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/Zephyr-latest/drivers/can/
Dcan_xmc4xxx.c93 const struct can_xmc4xxx_config *dev_cfg = dev->config; in can_xmc4xxx_set_mode() local
105 XMC_CAN_NODE_SetAnalyzerMode(dev_cfg->can); in can_xmc4xxx_set_mode()
107 XMC_CAN_NODE_ReSetAnalyzerMode(dev_cfg->can); in can_xmc4xxx_set_mode()
118 const struct can_xmc4xxx_config *dev_cfg = dev->config; in can_xmc4xxx_set_timing() local
131 reg = FIELD_PREP(CAN_NODE_NBTR_DIV8_Msk, dev_cfg->clock_div8); in can_xmc4xxx_set_timing()
137 dev_cfg->can->NBTR = reg; in can_xmc4xxx_set_timing()
278 const struct can_xmc4xxx_config *dev_cfg = dev->config; in can_xmc4xxx_init_fifo() local
295 CAN_XMC4XXX_REG_TO_NODE_IND(dev_cfg->can), mo_index); in can_xmc4xxx_init_fifo()
323 mo->MOIPR = FIELD_PREP(CAN_MO_MOIPR_RXINP_Msk, dev_cfg->service_request); in can_xmc4xxx_init_fifo()
331 CAN_XMC4XXX_REG_TO_NODE_IND(dev_cfg->can), mo_index); in can_xmc4xxx_init_fifo()
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/Zephyr-latest/drivers/sensor/qdec_sam/
Dqdec_sam.c40 const struct qdec_sam_dev_cfg *const dev_cfg = dev->config; in qdec_sam_fetch() local
42 Tc *const tc = dev_cfg->regs; in qdec_sam_fetch()
77 const struct qdec_sam_dev_cfg *const dev_cfg = dev->config; in qdec_sam_configure() local
78 Tc *const tc = dev_cfg->regs; in qdec_sam_configure()
98 const struct qdec_sam_dev_cfg *const dev_cfg = dev->config; in qdec_sam_initialize() local
102 retval = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT); in qdec_sam_initialize()
107 for (int i = 0; i < ARRAY_SIZE(dev_cfg->clock_cfg); i++) { in qdec_sam_initialize()
110 (clock_control_subsys_t)&dev_cfg->clock_cfg[i]); in qdec_sam_initialize()
/Zephyr-latest/drivers/flash/
Dflash_stm32_xspi.c127 const struct flash_stm32_xspi_config *dev_cfg = dev->config; in xspi_write_access() local
138 if ((dev_cfg->data_mode == XSPI_OCTO_MODE) && in xspi_write_access()
308 const struct flash_stm32_xspi_config *dev_cfg = dev->config; in stm32_xspi_read_sfdp() local
311 XSPI_RegularCmdTypeDef cmd = xspi_prepare_cmd(dev_cfg->data_mode, in stm32_xspi_read_sfdp()
312 dev_cfg->data_rate); in stm32_xspi_read_sfdp()
313 if (dev_cfg->data_mode == XSPI_OCTO_MODE) { in stm32_xspi_read_sfdp()
368 const struct flash_stm32_xspi_config *dev_cfg = dev->config; in xspi_address_is_valid() local
369 size_t flash_size = dev_cfg->flash_size; in xspi_address_is_valid()
407 const struct flash_stm32_xspi_config *dev_cfg = dev->config; in stm32_xspi_mem_erased() local
409 uint8_t nor_mode = dev_cfg->data_mode; in stm32_xspi_mem_erased()
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Dflash_stm32_ospi.c201 const struct flash_stm32_ospi_config *dev_cfg = dev->config; in ospi_send_cmd() local
214 LOG_DBG("CCR 0x%x", dev_cfg->regs->CCR); in ospi_send_cmd()
255 const struct flash_stm32_ospi_config *dev_cfg = dev->config; in ospi_write_access() local
266 if ((dev_cfg->data_mode == OSPI_OPI_MODE) && in ospi_write_access()
444 const struct flash_stm32_ospi_config *dev_cfg = dev->config; in stm32_ospi_read_sfdp() local
447 OSPI_RegularCmdTypeDef cmd = ospi_prepare_cmd(dev_cfg->data_mode, in stm32_ospi_read_sfdp()
448 dev_cfg->data_rate); in stm32_ospi_read_sfdp()
449 if (dev_cfg->data_mode == OSPI_OPI_MODE) { in stm32_ospi_read_sfdp()
495 const struct flash_stm32_ospi_config *dev_cfg = dev->config; in ospi_read_sfdp() local
504 memcpy(data, dev_cfg->sfdp_bfp + addr, size); in ospi_read_sfdp()
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/Zephyr-latest/drivers/i2s/
Di2s_mcux_sai.c141 const struct i2s_mcux_config *dev_cfg = dev->config; in i2s_tx_stream_disable() local
146 SAI_TxEnableDMA(dev_cfg->base, kSAI_FIFORequestDMAEnable, false); in i2s_tx_stream_disable()
151 while ((dev_cfg->base->TCSR & I2S_TCSR_FWF_MASK) == 0) { in i2s_tx_stream_disable()
156 dev_cfg->base->TCR3 &= ~I2S_TCR3_TCE_MASK; in i2s_tx_stream_disable()
159 SAI_TxEnable(dev_cfg->base, false); in i2s_tx_stream_disable()
162 if ((dev_cfg->base->TCSR & I2S_TCSR_TE_MASK) == 0UL) { in i2s_tx_stream_disable()
163 dev_cfg->base->TCSR |= (I2S_TCSR_FR_MASK | I2S_TCSR_SR_MASK); in i2s_tx_stream_disable()
164 dev_cfg->base->TCSR &= ~I2S_TCSR_SR_MASK; in i2s_tx_stream_disable()
178 const struct i2s_mcux_config *dev_cfg = dev->config; in i2s_rx_stream_disable() local
184 dev_cfg->base->RCR3 &= ~I2S_RCR3_RCE_MASK; in i2s_rx_stream_disable()
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/Zephyr-latest/drivers/i2c/
Di2c_sam_twihs_rtio.c94 const struct i2c_sam_twihs_dev_cfg *const dev_cfg = dev->config; in i2c_sam_twihs_configure() local
95 Twihs *const twihs = dev_cfg->regs; in i2c_sam_twihs_configure()
174 const struct i2c_sam_twihs_dev_cfg *const dev_cfg = dev->config; in i2c_sam_twihs_start() local
175 Twihs *const twihs = dev_cfg->regs; in i2c_sam_twihs_start()
204 const struct i2c_sam_twihs_dev_cfg *const dev_cfg = dev->config; in i2c_sam_twihs_complete() local
205 Twihs *const twihs = dev_cfg->regs; in i2c_sam_twihs_complete()
229 const struct i2c_sam_twihs_dev_cfg *const dev_cfg = dev->config; in i2c_sam_twihs_isr() local
231 Twihs *const twihs = dev_cfg->regs; in i2c_sam_twihs_isr()
290 const struct i2c_sam_twihs_dev_cfg *const dev_cfg = dev->config; in i2c_sam_twihs_initialize() local
292 Twihs *const twihs = dev_cfg->regs; in i2c_sam_twihs_initialize()
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