Searched refs:ctrl0 (Results 1 – 5 of 5) sorted by relevance
171 if (spi->ctrl0 & ADI_MAX32_SPI_CTRL_MASTER_MODE) { in spi_max32_setup()194 spi->ctrl0 |= MXC_F_SPI_CTRL0_EN; in spi_max32_setup()221 if (!(spi->ctrl0 & MXC_F_SPI_CTRL0_START)) { in spi_max32_transceive_sync()222 spi->ctrl0 |= MXC_F_SPI_CTRL0_START; in spi_max32_transceive_sync()384 cfg->regs->ctrl0 = in transceive()385 (cfg->regs->ctrl0 & ~MXC_F_SPI_CTRL0_START) | MXC_F_SPI_CTRL0_SS_CTRL; in transceive()415 cfg->regs->ctrl0 &= ~(MXC_F_SPI_CTRL0_START | MXC_F_SPI_CTRL0_SS_CTRL | in transceive()417 cfg->regs->ctrl0 |= MXC_F_SPI_CTRL0_EN; in transceive()574 spi->ctrl0 = (spi->ctrl0 & ~MXC_F_SPI_CTRL0_START) | MXC_F_SPI_CTRL0_SS_CTRL; in transceive_dma()623 spi->ctrl0 &= in transceive_dma()[all …]
48 uint8_t ctrl0; member206 uart->ctrl0 = bwpc; in uart_b91_init()425 uart->ctrl0 |= UART_TX_IRQ_MASK; in uart_b91_irq_tx_enable()433 uart->ctrl0 &= ~UART_TX_IRQ_MASK; in uart_b91_irq_tx_disable()442 ((uart->ctrl0 & UART_TX_IRQ_MASK) != 0)) ? 1 : 0; in uart_b91_irq_tx_ready()460 uart->ctrl0 |= UART_RX_IRQ_MASK; in uart_b91_irq_rx_enable()468 uart->ctrl0 &= ~UART_RX_IRQ_MASK; in uart_b91_irq_rx_disable()
101 uint8_t ctrl0; member342 if ((data->reg.ctrl0 & CTRL0_AIE) != 0) { in rx8130ce_alarm_set_time()344 data->reg.ctrl0 &= ~CTRL0_AIE; in rx8130ce_alarm_set_time()355 data->reg.ctrl0 |= CTRL0_AIE; in rx8130ce_alarm_set_time()462 rc = (data->reg.ctrl0 & CTRL0_AIE) != 0; in rx8130ce_alarm_is_pending()493 data->reg.ctrl0 &= ~CTRL0_AIE; in rx8130ce_alarm_set_callback()507 data->reg.ctrl0 |= CTRL0_AIE; in rx8130ce_alarm_set_callback()548 data->reg.ctrl0 &= ~CTRL0_UIE; in rx8130ce_update_set_callback()564 data->reg.ctrl0 |= CTRL0_UIE; in rx8130ce_update_set_callback()
30 &ctrl0 {
37 ctrl0: soc_controller@e0000000 { label
