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Searched refs:clk_cfg (Results 1 – 25 of 25) sorted by relevance

/Zephyr-latest/tests/boards/espressif/rtc_clk/src/
Drtc_clk_test.c51 struct esp32_clock_config clk_cfg = {0}; in ZTEST() local
55 clk_cfg.cpu.clk_src = ESP32_CPU_CLK_SRC_XTAL; in ZTEST()
56 clk_cfg.cpu.xtal_freq = (DT_PROP(DT_INST(0, DT_CPU_COMPAT), xtal_freq) / MHZ(1)); in ZTEST()
59 clk_cfg.cpu.cpu_freq = clk_cfg.cpu.xtal_freq >> i; in ZTEST()
61 TC_PRINT("Testing CPU frequency: %d MHz\n", clk_cfg.cpu.cpu_freq); in ZTEST()
64 clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_CPU, &clk_cfg); in ZTEST()
70 zassert_equal(cpu_rate, clk_cfg.cpu.cpu_freq * MHZ(1), in ZTEST()
72 clk_cfg.cpu.cpu_freq); in ZTEST()
91 struct esp32_clock_config clk_cfg = {0}; in ZTEST() local
95 clk_cfg.cpu.clk_src = ESP32_CPU_CLK_SRC_PLL; in ZTEST()
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/Zephyr-latest/drivers/clock_control/
Dclock_control_nrf2_hsfll.c50 STRUCT_CLOCK_CONFIG(hsfll, ARRAY_SIZE(clock_options)) clk_cfg;
63 prev_flags = atomic_and(&dev_data->clk_cfg.flags, in freq_setting_applied_cb()
68 clock_config_update_end(&dev_data->clk_cfg, 0); in freq_setting_applied_cb()
77 clock_config_update_end(&dev_data->clk_cfg, -ETIMEDOUT); in hsfll_update_timeout_handler()
83 CONTAINER_OF(work, struct hsfll_dev_data, clk_cfg.work); in hsfll_work_handler()
94 clock_config_update_end(&dev_data->clk_cfg, rc); in hsfll_work_handler()
99 (void)atomic_or(&dev_data->clk_cfg.flags, FLAG_FREQ_CHANGE_CB_EXPECTED); in hsfll_work_handler()
110 return &dev_data->clk_cfg.onoff[0].mgr; in hsfll_find_mgr()
127 return &dev_data->clk_cfg.onoff[i].mgr; in hsfll_find_mgr()
191 rc = clock_config_init(&dev_data->clk_cfg, in hsfll_init()
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Dclock_control_nrf2_fll16m.c57 STRUCT_CLOCK_CONFIG(fll16m, ARRAY_SIZE(clock_options)) clk_cfg;
82 clock_config_update_end(&dev_data->clk_cfg, 0); in activate_fll16m_mode()
97 clock_config_update_end(&dev_data->clk_cfg, res); in hfxo_cb()
99 (void)atomic_or(&dev_data->clk_cfg.flags, FLAG_HFXO_STARTED); in hfxo_cb()
109 CONTAINER_OF(work, struct fll16m_dev_data, clk_cfg.work); in fll16m_work_handler()
120 clock_config_update_end(&dev_data->clk_cfg, rc); in fll16m_work_handler()
125 prev_flags = atomic_and(&dev_data->clk_cfg.flags, in fll16m_work_handler()
144 return &dev_data->clk_cfg.onoff[0].mgr; in fll16m_find_mgr()
167 return &dev_data->clk_cfg.onoff[i].mgr; in fll16m_find_mgr()
250 return clock_config_init(&dev_data->clk_cfg, in fll16m_init()
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Dclock_control_npcx.c38 struct npcx_clk_cfg *clk_cfg = (struct npcx_clk_cfg *)(sub_system); in npcx_clock_control_on() local
41 if (clk_cfg->ctrl >= NPCX_PWDWN_CTL_COUNT) { in npcx_clock_control_on()
46 NPCX_PWDWN_CTL(pmc_base, clk_cfg->ctrl) &= ~(BIT(clk_cfg->bit)); in npcx_clock_control_on()
54 struct npcx_clk_cfg *clk_cfg = (struct npcx_clk_cfg *)(sub_system); in npcx_clock_control_off() local
57 if (clk_cfg->ctrl >= NPCX_PWDWN_CTL_COUNT) { in npcx_clock_control_off()
62 NPCX_PWDWN_CTL(pmc_base, clk_cfg->ctrl) |= BIT(clk_cfg->bit); in npcx_clock_control_off()
71 struct npcx_clk_cfg *clk_cfg = (struct npcx_clk_cfg *)(sub_system); in npcx_clock_control_get_subsys_rate() local
73 switch (clk_cfg->bus) { in npcx_clock_control_get_subsys_rate()
Dclock_control_nrf2_global_hsfll.c47 STRUCT_CLOCK_CONFIG(global_hsfll, GLOBAL_HSFLL_CLOCK_FREQUENCIES_SIZE) clk_cfg;
73 return &dev_data->clk_cfg.onoff[0].mgr; in global_hsfll_find_mgr()
90 return &dev_data->clk_cfg.onoff[i].mgr; in global_hsfll_find_mgr()
174 CONTAINER_OF(work, struct global_hsfll_dev_data, clk_cfg.work); in global_hsfll_work_handler()
186 clock_config_update_end(&dev_data->clk_cfg, -EIO); in global_hsfll_work_handler()
201 clock_config_update_end(&dev_data->clk_cfg, rc); in global_hsfll_evt_handler()
232 clock_config_update_end(&dev_data->clk_cfg, -ETIMEDOUT); in global_hsfll_timeout_handler()
270 rc = clock_config_init(&dev_data->clk_cfg, in global_hfsll_init()
271 ARRAY_SIZE(dev_data->clk_cfg.onoff), in global_hfsll_init()
Dclock_control_nrf2_lfclk.c58 STRUCT_CLOCK_CONFIG(lfclk, ARRAY_SIZE(clock_options)) clk_cfg;
79 clock_config_update_end(&dev_data->clk_cfg, status); in clock_evt_handler()
87 clock_config_update_end(&dev_data->clk_cfg, -ETIMEDOUT); in lfclk_update_timeout_handler()
93 CONTAINER_OF(work, struct lfclk_dev_data, clk_cfg.work); in lfclk_work_handler()
102 clock_config_update_end(&dev_data->clk_cfg, -EIO); in lfclk_work_handler()
116 return &dev_data->clk_cfg.onoff[0].mgr; in lfclk_find_mgr()
135 return &dev_data->clk_cfg.onoff[i].mgr; in lfclk_find_mgr()
258 return clock_config_init(&dev_data->clk_cfg, in lfclk_init()
259 ARRAY_SIZE(dev_data->clk_cfg.onoff), in lfclk_init()
Dclock_control_nrf2_common.h60 int clock_config_init(void *clk_cfg, uint8_t onoff_cnt, k_work_handler_t update_work_handler);
84 void clock_config_update_end(void *clk_cfg, int status);
Dclock_control_nrf2_common.c123 int clock_config_init(void *clk_cfg, uint8_t onoff_cnt, k_work_handler_t update_work_handler) in clock_config_init() argument
125 struct clock_config_generic *cfg = clk_cfg; in clock_config_init()
164 void clock_config_update_end(void *clk_cfg, int status) in clock_config_update_end() argument
166 struct clock_config_generic *cfg = clk_cfg; in clock_config_update_end()
Dclock_control_npcm.c142 static struct clk_cfg_t clk_cfg[] = { variable
201 for (i = 0; i < ARRAY_SIZE(clk_cfg); i++) { in npcm_get_cfg()
202 if (clk_cfg[i].clock_id == clk_id) { in npcm_get_cfg()
203 return &clk_cfg[i]; in npcm_get_cfg()
/Zephyr-latest/drivers/pwm/
Dpwm_npcx.c41 struct npcx_clk_cfg clk_cfg; member
194 &config->clk_cfg); in pwm_npcx_init()
201 &config->clk_cfg, &data->cycles_per_sec); in pwm_npcx_init()
208 pwm_npcx_configure(dev, config->clk_cfg.bus); in pwm_npcx_init()
225 .clk_cfg = NPCX_DT_CLK_CFG_ITEM(inst), \
/Zephyr-latest/soc/mediatek/mt8xxx/
Dcpuclk.c46 } clk_cfg[29]; member
113 MTK_CLK_GEN.clk_cfg[clk].clr = (0xf << shift); in setclk()
115 MTK_CLK_GEN.clk_cfg[clk].set = (val << shift); in setclk()
/Zephyr-latest/drivers/watchdog/
Dxt_wdt_esp32.c103 struct esp32_clock_config clk_cfg = {0}; in esp32_xt_wdt_isr() local
112 clk_cfg.rtc.rtc_slow_clock_src = ESP32_RTC_SLOW_CLK_SRC_RC_SLOW; in esp32_xt_wdt_isr()
116 &clk_cfg); in esp32_xt_wdt_isr()
/Zephyr-latest/drivers/i2c/
Di2c_renesas_ra_iic.c48 iic_master_clock_settings_t *clk_cfg);
355 iic_master_clock_settings_t *clk_cfg) in calc_iic_master_clock_setting() argument
468 clk_cfg->brl_value = bitrate.brl; in calc_iic_master_clock_setting()
469 clk_cfg->brh_value = bitrate.brh; in calc_iic_master_clock_setting()
470 clk_cfg->cks_value = bitrate.divider; in calc_iic_master_clock_setting()
473 clk_cfg->brl_value, clk_cfg->brh_value, clk_cfg->cks_value); in calc_iic_master_clock_setting()
Di2c_npcx_controller.c146 struct npcx_clk_cfg clk_cfg; /* clock configuration */ member
1260 (clock_control_subsys_t) &config->clk_cfg) != 0) { in i2c_ctrl_init()
1271 &config->clk_cfg, &i2c_rate) != 0) { in i2c_ctrl_init()
1325 .clk_cfg = NPCX_DT_CLK_CFG_ITEM(inst), \
/Zephyr-latest/drivers/input/
Dinput_npcx_kbd.c31 struct npcx_clk_cfg clk_cfg; member
154 ret = clock_control_on(clk_dev, (clock_control_subsys_t)&config->clk_cfg); in npcx_kbd_init()
221 .clk_cfg = NPCX_DT_CLK_CFG_ITEM(0),
/Zephyr-latest/drivers/peci/
Dpeci_npcx.c28 struct npcx_clk_cfg clk_cfg; member
247 ret = clock_control_on(clk_dev, (clock_control_subsys_t)&config->clk_cfg); in peci_npcx_init()
253 ret = clock_control_get_rate(clk_dev, (clock_control_subsys_t)&config->clk_cfg, in peci_npcx_init()
282 .clk_cfg = NPCX_DT_CLK_CFG_ITEM(0),
/Zephyr-latest/drivers/sensor/nuvoton/nuvoton_tach_npcx/
Dtach_nuvoton_npcx.c58 struct npcx_clk_cfg clk_cfg; member
326 &config->clk_cfg); in tach_npcx_init()
333 &config->clk_cfg, &data->input_clk); in tach_npcx_init()
376 .clk_cfg = NPCX_DT_CLK_CFG_ITEM(inst), \
/Zephyr-latest/drivers/ps2/
Dps2_npcx_controller.c48 struct npcx_clk_cfg clk_cfg; member
322 .clk_cfg = NPCX_DT_CLK_CFG_ITEM(0),
344 (clock_control_subsys_t)&config->clk_cfg); in ps2_npcx_ctrl_init()
364 if (config->clk_cfg.bus == NPCX_CLOCK_BUS_FREERUN) { in ps2_npcx_ctrl_init()
/Zephyr-latest/drivers/flash/
Dflash_npcx_fiu_qspi.c30 struct npcx_clk_cfg clk_cfg; member
261 (clock_control_subsys_t)&config->clk_cfg); in qspi_npcx_fiu_init()
285 .clk_cfg = NPCX_DT_CLK_CFG_ITEM(n), \
/Zephyr-latest/drivers/spi/
Dspi_npcx_spip.c35 struct npcx_clk_cfg clk_cfg; member
369 ret = clock_control_on(clk_dev, (clock_control_subsys_t)&config->clk_cfg); in spi_npcx_spip_init()
375 ret = clock_control_get_rate(clk_dev, (clock_control_subsys_t)&config->clk_cfg, in spi_npcx_spip_init()
442 .clk_cfg = NPCX_DT_CLK_CFG_ITEM(n), \
/Zephyr-latest/drivers/bluetooth/hci/
Dipm_stm32wb.c28 static const struct stm32_pclken clk_cfg[] = STM32_DT_CLOCKS(DT_DRV_INST(0)); variable
502 err = clock_control_configure(clk, (clock_control_subsys_t) &clk_cfg[1], in c2_reset()
520 err = clock_control_on(clk, (clock_control_subsys_t) &clk_cfg[0]); in c2_reset()
537 stm32wb_start_ble(clk_cfg[1].bus); in c2_reset()
/Zephyr-latest/subsys/mgmt/ec_host_cmd/backends/
Dec_host_cmd_backend_shi_npcx.c114 struct npcx_clk_cfg clk_cfg; member
837 ret = clock_control_on(clk_dev, (clock_control_subsys_t)&config->clk_cfg); in shi_npcx_enable()
884 ret = clock_control_off(clk_dev, (clock_control_subsys_t)&config->clk_cfg); in shi_npcx_disable()
924 ret = clock_control_on(clk_dev, (clock_control_subsys_t)&config->clk_cfg); in shi_npcx_init_registers()
1135 .clk_cfg = NPCX_DT_CLK_CFG_ITEM(0),
/Zephyr-latest/drivers/adc/
Dadc_npcx.c49 struct npcx_clk_cfg clk_cfg; member
789 &config->clk_cfg); in adc_npcx_init()
796 &config->clk_cfg, &data->input_clk); in adc_npcx_init()
856 .clk_cfg = NPCX_DT_CLK_CFG_ITEM(n), \
/Zephyr-latest/drivers/serial/
Duart_npcx.c32 struct npcx_clk_cfg clk_cfg; member
1023 ret = clock_control_on(clk_dev, (clock_control_subsys_t)&config->clk_cfg); in uart_npcx_init()
1041 ret = clock_control_get_rate(clk_dev, (clock_control_subsys_t)&config->clk_cfg, &uart_rate); in uart_npcx_init()
1135 .clk_cfg = NPCX_DT_CLK_CFG_ITEM(i), \
/Zephyr-latest/drivers/espi/
Despi_npcx.c31 struct npcx_clk_cfg clk_cfg; member
1378 .clk_cfg = NPCX_DT_CLK_CFG_ITEM(0),
1402 &config->clk_cfg); in espi_npcx_init()