1 /*
2 * Copyright (c) 2024 Nordic Semiconductor ASA
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6 #define DT_DRV_COMPAT nordic_nrf_fll16m
7
8 #include "clock_control_nrf2_common.h"
9 #include <zephyr/devicetree.h>
10 #include <zephyr/drivers/clock_control/nrf_clock_control.h>
11
12 #include <soc_lrcconf.h>
13 #include <hal/nrf_bicr.h>
14
15 #include <zephyr/logging/log.h>
16 LOG_MODULE_DECLARE(clock_control_nrf2, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
17
18 BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
19 "multiple instances not supported");
20
21 #define FLAG_HFXO_STARTED BIT(FLAGS_COMMON_BITS)
22
23 #define FLL16M_MODE_OPEN_LOOP 0
24 #define FLL16M_MODE_CLOSED_LOOP 1
25 #define FLL16M_MODE_BYPASS 2
26 #define FLL16M_MODE_DEFAULT FLL16M_MODE_OPEN_LOOP
27
28 #define FLL16M_HFXO_NODE DT_INST_PHANDLE_BY_NAME(0, clocks, hfxo)
29
30 #define FLL16M_HFXO_ACCURACY DT_PROP(FLL16M_HFXO_NODE, accuracy_ppm)
31 #define FLL16M_OPEN_LOOP_ACCURACY DT_INST_PROP(0, open_loop_accuracy_ppm)
32 #define FLL16M_CLOSED_LOOP_BASE_ACCURACY DT_INST_PROP(0, closed_loop_base_accuracy_ppm)
33 #define FLL16M_MAX_ACCURACY FLL16M_HFXO_ACCURACY
34
35 #define BICR (NRF_BICR_Type *)DT_REG_ADDR(DT_NODELABEL(bicr))
36
37 /* Clock options sorted from lowest to highest accuracy */
38 static struct clock_options {
39 uint16_t accuracy;
40 uint8_t mode;
41 } clock_options[] = {
42 {
43 .accuracy = FLL16M_OPEN_LOOP_ACCURACY,
44 .mode = FLL16M_MODE_OPEN_LOOP,
45 },
46 {
47 .mode = FLL16M_MODE_CLOSED_LOOP,
48 },
49 {
50 /* Bypass mode uses HFXO */
51 .accuracy = FLL16M_HFXO_ACCURACY,
52 .mode = FLL16M_MODE_BYPASS,
53 },
54 };
55
56 struct fll16m_dev_data {
57 STRUCT_CLOCK_CONFIG(fll16m, ARRAY_SIZE(clock_options)) clk_cfg;
58 struct onoff_client hfxo_cli;
59 sys_snode_t fll16m_node;
60 };
61
62 struct fll16m_dev_config {
63 uint32_t fixed_frequency;
64 };
65
activate_fll16m_mode(struct fll16m_dev_data * dev_data,uint8_t mode)66 static void activate_fll16m_mode(struct fll16m_dev_data *dev_data, uint8_t mode)
67 {
68 /* TODO: change to nrf_lrcconf_* function when such is available. */
69
70 if (mode != FLL16M_MODE_DEFAULT) {
71 soc_lrcconf_poweron_request(&dev_data->fll16m_node, NRF_LRCCONF_POWER_MAIN);
72 }
73
74 NRF_LRCCONF010->CLKCTRL[0].SRC = mode;
75
76 if (mode == FLL16M_MODE_DEFAULT) {
77 soc_lrcconf_poweron_release(&dev_data->fll16m_node, NRF_LRCCONF_POWER_MAIN);
78 }
79
80 nrf_lrcconf_task_trigger(NRF_LRCCONF010, NRF_LRCCONF_TASK_CLKSTART_0);
81
82 clock_config_update_end(&dev_data->clk_cfg, 0);
83 }
84
hfxo_cb(struct onoff_manager * mgr,struct onoff_client * cli,uint32_t state,int res)85 static void hfxo_cb(struct onoff_manager *mgr,
86 struct onoff_client *cli,
87 uint32_t state,
88 int res)
89 {
90 ARG_UNUSED(mgr);
91 ARG_UNUSED(state);
92
93 struct fll16m_dev_data *dev_data =
94 CONTAINER_OF(cli, struct fll16m_dev_data, hfxo_cli);
95
96 if (res < 0) {
97 clock_config_update_end(&dev_data->clk_cfg, res);
98 } else {
99 (void)atomic_or(&dev_data->clk_cfg.flags, FLAG_HFXO_STARTED);
100
101 activate_fll16m_mode(dev_data, FLL16M_MODE_BYPASS);
102 }
103 }
104
fll16m_work_handler(struct k_work * work)105 static void fll16m_work_handler(struct k_work *work)
106 {
107 const struct device *hfxo = DEVICE_DT_GET(FLL16M_HFXO_NODE);
108 struct fll16m_dev_data *dev_data =
109 CONTAINER_OF(work, struct fll16m_dev_data, clk_cfg.work);
110 uint8_t to_activate_idx;
111
112 to_activate_idx = clock_config_update_begin(work);
113 if (clock_options[to_activate_idx].mode == FLL16M_MODE_BYPASS) {
114 int rc;
115
116 /* Bypass mode requires HFXO to be running first. */
117 sys_notify_init_callback(&dev_data->hfxo_cli.notify, hfxo_cb);
118 rc = nrf_clock_control_request(hfxo, NULL, &dev_data->hfxo_cli);
119 if (rc < 0) {
120 clock_config_update_end(&dev_data->clk_cfg, rc);
121 }
122 } else {
123 atomic_val_t prev_flags;
124
125 prev_flags = atomic_and(&dev_data->clk_cfg.flags,
126 ~FLAG_HFXO_STARTED);
127 if (prev_flags & FLAG_HFXO_STARTED) {
128 (void)nrf_clock_control_release(hfxo, NULL);
129 }
130
131 activate_fll16m_mode(dev_data,
132 clock_options[to_activate_idx].mode);
133 }
134 }
135
fll16m_find_mgr(const struct device * dev,const struct nrf_clock_spec * spec)136 static struct onoff_manager *fll16m_find_mgr(const struct device *dev,
137 const struct nrf_clock_spec *spec)
138 {
139 struct fll16m_dev_data *dev_data = dev->data;
140 const struct fll16m_dev_config *dev_config = dev->config;
141 uint16_t accuracy;
142
143 if (!spec) {
144 return &dev_data->clk_cfg.onoff[0].mgr;
145 }
146
147 if (spec->frequency > dev_config->fixed_frequency) {
148 LOG_ERR("invalid frequency");
149 return NULL;
150 }
151
152 if (spec->precision) {
153 LOG_ERR("invalid precision");
154 return NULL;
155 }
156
157 accuracy = spec->accuracy == NRF_CLOCK_CONTROL_ACCURACY_MAX
158 ? FLL16M_MAX_ACCURACY
159 : spec->accuracy;
160
161 for (int i = 0; i < ARRAY_SIZE(clock_options); ++i) {
162 if (accuracy &&
163 accuracy < clock_options[i].accuracy) {
164 continue;
165 }
166
167 return &dev_data->clk_cfg.onoff[i].mgr;
168 }
169
170 LOG_ERR("invalid accuracy");
171 return NULL;
172 }
173
api_request_fll16m(const struct device * dev,const struct nrf_clock_spec * spec,struct onoff_client * cli)174 static int api_request_fll16m(const struct device *dev,
175 const struct nrf_clock_spec *spec,
176 struct onoff_client *cli)
177 {
178 struct onoff_manager *mgr = fll16m_find_mgr(dev, spec);
179
180 if (mgr) {
181 return onoff_request(mgr, cli);
182 }
183
184 return -EINVAL;
185 }
186
api_release_fll16m(const struct device * dev,const struct nrf_clock_spec * spec)187 static int api_release_fll16m(const struct device *dev,
188 const struct nrf_clock_spec *spec)
189 {
190 struct onoff_manager *mgr = fll16m_find_mgr(dev, spec);
191
192 if (mgr) {
193 return onoff_release(mgr);
194 }
195
196 return -EINVAL;
197 }
198
api_cancel_or_release_fll16m(const struct device * dev,const struct nrf_clock_spec * spec,struct onoff_client * cli)199 static int api_cancel_or_release_fll16m(const struct device *dev,
200 const struct nrf_clock_spec *spec,
201 struct onoff_client *cli)
202 {
203 struct onoff_manager *mgr = fll16m_find_mgr(dev, spec);
204
205 if (mgr) {
206 return onoff_cancel_or_release(mgr, cli);
207 }
208
209 return -EINVAL;
210 }
211
api_get_rate_fll16m(const struct device * dev,clock_control_subsys_t sys,uint32_t * rate)212 static int api_get_rate_fll16m(const struct device *dev,
213 clock_control_subsys_t sys,
214 uint32_t *rate)
215 {
216 ARG_UNUSED(sys);
217
218 const struct fll16m_dev_config *dev_config = dev->config;
219
220 *rate = dev_config->fixed_frequency;
221
222 return 0;
223 }
224
fll16m_init(const struct device * dev)225 static int fll16m_init(const struct device *dev)
226 {
227 struct fll16m_dev_data *dev_data = dev->data;
228 nrf_bicr_lfosc_mode_t lfosc_mode;
229
230 clock_options[1].accuracy = FLL16M_CLOSED_LOOP_BASE_ACCURACY;
231
232 /* Closed-loop mode uses LFXO as source if present, HFXO otherwise */
233 lfosc_mode = nrf_bicr_lfosc_mode_get(BICR);
234
235 if (lfosc_mode != NRF_BICR_LFOSC_MODE_UNCONFIGURED &&
236 lfosc_mode != NRF_BICR_LFOSC_MODE_DISABLED) {
237 int ret;
238 uint16_t accuracy;
239
240 ret = lfosc_get_accuracy(&accuracy);
241 if (ret < 0) {
242 return ret;
243 }
244
245 clock_options[1].accuracy += accuracy;
246 } else {
247 clock_options[1].accuracy += FLL16M_HFXO_ACCURACY;
248 }
249
250 return clock_config_init(&dev_data->clk_cfg,
251 ARRAY_SIZE(dev_data->clk_cfg.onoff),
252 fll16m_work_handler);
253 }
254
255 static DEVICE_API(nrf_clock_control, fll16m_drv_api) = {
256 .std_api = {
257 .on = api_nosys_on_off,
258 .off = api_nosys_on_off,
259 .get_rate = api_get_rate_fll16m,
260 },
261 .request = api_request_fll16m,
262 .release = api_release_fll16m,
263 .cancel_or_release = api_cancel_or_release_fll16m,
264 };
265
266 static struct fll16m_dev_data fll16m_data;
267
268 static const struct fll16m_dev_config fll16m_config = {
269 .fixed_frequency = DT_INST_PROP(0, clock_frequency),
270 };
271
272 DEVICE_DT_INST_DEFINE(0, fll16m_init, NULL,
273 &fll16m_data, &fll16m_config,
274 PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
275 &fll16m_drv_api);
276
