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/Zephyr-latest/tests/boards/intel_adsp/cache/src/
Dmain.c13 uint32_t *cached, *uncached; in ZTEST() local
15 cached = (uint32_t *)LP_SRAM_BASE; in ZTEST()
16 uncached = sys_cache_uncached_ptr_get(cached); in ZTEST()
18 *cached = 42; in ZTEST()
22 zassert_equal(*cached, 42, NULL); in ZTEST()
28 zassert_equal(*cached, 42, NULL); in ZTEST()
36 zassert_equal(*cached, 80, NULL); in ZTEST()
39 *cached = 82; in ZTEST()
42 zassert_equal(*cached, 82, NULL); in ZTEST()
48 zassert_equal(*cached, 82, NULL); in ZTEST()
[all …]
/Zephyr-latest/arch/xtensa/core/
Dmem_manage.c16 uintptr_t cached = (uintptr_t)sys_cache_cached_ptr_get((void *)phys); in sys_mm_is_phys_addr_in_range() local
21 valid |= ((cached >= CONFIG_SRAM_BASE_ADDRESS) && in sys_mm_is_phys_addr_in_range()
22 (cached < (CONFIG_SRAM_BASE_ADDRESS + (CONFIG_SRAM_SIZE * 1024UL)))); in sys_mm_is_phys_addr_in_range()
32 uintptr_t cached = (uintptr_t)sys_cache_cached_ptr_get(virt); in sys_mm_is_virt_addr_in_range() local
37 valid |= ((cached >= CONFIG_KERNEL_VM_BASE) && in sys_mm_is_virt_addr_in_range()
38 (cached < (CONFIG_KERNEL_VM_BASE + CONFIG_KERNEL_VM_SIZE))); in sys_mm_is_virt_addr_in_range()
/Zephyr-latest/subsys/logging/
Dlog_mgmt.c214 uint8_t *cached; in link_source_name_get() local
224 if (!log_cache_get(&sname_cache, id.raw, &cached)) { in link_source_name_get()
232 cached, &cache_size); in link_source_name_get()
237 log_cache_put(&sname_cache, cached); in link_source_name_get()
240 return (const char *)cached; in link_source_name_get()
266 uint8_t *cached; in link_domain_name_get() local
272 if (!log_cache_get(&dname_cache, id, &cached)) { in link_domain_name_get()
279 err = log_link_get_domain_name(link, rel_domain_id, cached, &cache_size); in link_domain_name_get()
281 log_cache_release(&dname_cache, cached); in link_domain_name_get()
285 log_cache_put(&dname_cache, cached); in link_domain_name_get()
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/Zephyr-latest/soc/aspeed/ast10x0/
DKconfig22 The non-cached SRAM size in kB. The default value comes from reg[1]
29 The non-cached SRAM base address. The default value comes from
/Zephyr-latest/doc/develop/sca/
Dsparse.rst14 ``__cache`` used to identify pointers from the cached address range on the
15 Xtensa architecture. This helps identify cases where cached and uncached
/Zephyr-latest/tests/kernel/mp/
DKconfig6 # the shared variables in cached/incoherent memory.
/Zephyr-latest/soc/mediatek/mt8xxx/
DCMakeLists.txt19 # RIMAGE_TARGET cached (cached so that the python script can read it!)
23 # a RIMAGE_CONFIG_PATH cmake cached (!) variable set to a directory
/Zephyr-latest/boards/nxp/mr_canhubk3/
Dmr_canhubk3_defconfig15 # Use no-cached memory for HAL
/Zephyr-latest/arch/common/
Dnocache.ld10 /* Non-cached region of RAM */
/Zephyr-latest/boards/shields/st_b_lcd40_dsi1_mb1166/boards/
Dstm32h747i_disco_stm32h747xx_m7.overlay8 /* Frame buffer memory when cached causes screen flickering. */
/Zephyr-latest/subsys/settings/src/
Dsettings_nvs.c135 uint16_t cached = 0; in settings_nvs_load() local
148 cf->cache_total = cached; in settings_nvs_load()
201 cached++; in settings_nvs_load()
/Zephyr-latest/drivers/gpio/
DKconfig.pca_series39 When disabled, only output registers will be cached.
/Zephyr-latest/boards/nxp/mimxrt1160_evk/
Dmimxrt1160_evk_mimxrt1166_cm4.dts19 * a memory region that is not cached by the chip. If the chosen
/Zephyr-latest/boards/nxp/mimxrt1170_evk/
Dmimxrt1170_evk_mimxrt1176_cm4.dts19 * a memory region that is not cached by the chip. If the chosen
/Zephyr-latest/soc/intel/intel_adsp/cavs/include/
Dxtensa-cavs-linker.ld389 /* This section is cached. By default it contains only declared
392 .cached SEGSTART_CACHED : {
394 *(.cached .cached.*)
444 /* Non-loadable sections below. Back to cached memory so
/Zephyr-latest/include/zephyr/linker/
Dsection_tags.h62 #define __incoherent __in_section_unique(cached)
/Zephyr-latest/arch/xtensa/
DKconfig63 so that it can be seen in both (incoherent) cached mappings
72 Region Protection Option) contains the "cached" mapping.
221 bool "Map memory in cached and uncached region"
224 distinct region, cached and uncached.
/Zephyr-latest/arch/arc/
DCMakeLists.txt17 # Instruct compiler to use proper register as cached thread pointer for thread local storage.
/Zephyr-latest/soc/intel/intel_adsp/ace/
Dace-link.ld478 /* This section is cached. By default it contains only declared
481 .cached SEGSTART_CACHED : {
483 *(.cached .cached.*)
559 /* Non-loadable sections below. Back to cached memory so
/Zephyr-latest/drivers/usb/udc/
DKconfig33 cannot handle buffers in cached memory.
/Zephyr-latest/soc/nxp/imxrt/
DKconfig106 an MPU region will be defined to disable cached access to the
114 or an MPU region will be defined to disable cached access to the
/Zephyr-latest/subsys/bluetooth/controller/ll_sw/
Dull_conn_types.h78 struct pdu_data_llctrl_version_ind cached; member
Dull_llcp_pdu.c295 p->version_number = conn->llcp.vex.cached.version_number; in llcp_ntf_encode_version_ind()
296 p->company_id = sys_cpu_to_le16(conn->llcp.vex.cached.company_id); in llcp_ntf_encode_version_ind()
297 p->sub_version_number = sys_cpu_to_le16(conn->llcp.vex.cached.sub_version_number); in llcp_ntf_encode_version_ind()
303 conn->llcp.vex.cached.version_number = pdu->llctrl.version_ind.version_number; in llcp_pdu_decode_version_ind()
304 conn->llcp.vex.cached.company_id = sys_le16_to_cpu(pdu->llctrl.version_ind.company_id); in llcp_pdu_decode_version_ind()
305 conn->llcp.vex.cached.sub_version_number = in llcp_pdu_decode_version_ind()
/Zephyr-latest/cmake/modules/
DFindHostTools.cmake106 # Set cached ZEPHYR_TOOLCHAIN_VARIANT.
/Zephyr-latest/tests/cmake/zephyr_get/
DCMakeLists.txt114 # Environment value is cached after it's retrieved.
195 # Environment is not cached when using MERGE.
340 # If an environment value wins, it is cached afterwards.
575 # If an environment value wins, it gets cached and promoted above snippets.

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