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/Zephyr-latest/subsys/net/lib/dns/
Ddns_cache.c12 static void dns_cache_clean(struct dns_cache const *cache);
14 int dns_cache_flush(struct dns_cache *cache) in dns_cache_flush() argument
16 k_mutex_lock(cache->lock, K_FOREVER); in dns_cache_flush()
17 for (size_t i = 0; i < cache->size; i++) { in dns_cache_flush()
18 cache->entries[i].in_use = false; in dns_cache_flush()
20 k_mutex_unlock(cache->lock); in dns_cache_flush()
25 int dns_cache_add(struct dns_cache *cache, char const *query, struct dns_addrinfo const *addrinfo, in dns_cache_add() argument
32 if (cache == NULL || query == NULL || addrinfo == NULL || ttl == 0) { in dns_cache_add()
43 k_mutex_lock(cache->lock, K_FOREVER); in dns_cache_add()
47 dns_cache_clean(cache); in dns_cache_add()
[all …]
Ddns_cache.h56 int dns_cache_flush(struct dns_cache *cache);
71 int dns_cache_add(struct dns_cache *cache, char const *query, struct dns_addrinfo const *addrinfo,
82 int dns_cache_remove(struct dns_cache *cache, char const *query);
97 int dns_cache_find(struct dns_cache const *cache, const char *query, struct dns_addrinfo *addrinfo,
/Zephyr-latest/subsys/logging/
Dlog_cache.c24 int log_cache_init(struct log_cache *cache, const struct log_cache_config *config) in log_cache_init() argument
26 sys_slist_init(&cache->active); in log_cache_init()
27 sys_slist_init(&cache->idle); in log_cache_init()
41 sys_slist_append(&cache->idle, &entry->node); in log_cache_init()
45 cache->cmp = config->cmp; in log_cache_init()
46 cache->item_size = config->item_size; in log_cache_init()
47 cache->hit = 0; in log_cache_init()
48 cache->miss = 0; in log_cache_init()
53 bool log_cache_get(struct log_cache *cache, uintptr_t id, uint8_t **data) in log_cache_get() argument
60 SYS_SLIST_FOR_EACH_CONTAINER(&cache->active, entry, node) { in log_cache_get()
[all …]
Dlog_cache.h39 int log_cache_init(struct log_cache *cache, const struct log_cache_config *config);
50 bool log_cache_get(struct log_cache *cache, uintptr_t id, uint8_t **data);
58 void log_cache_put(struct log_cache *cache, uint8_t *data);
68 void log_cache_release(struct log_cache *cache, uint8_t *data);
76 static inline uint32_t log_cache_get_hit(struct log_cache *cache) in log_cache_get_hit() argument
78 return cache->hit; in log_cache_get_hit()
87 static inline uint32_t log_cache_get_miss(struct log_cache *cache) in log_cache_get_miss() argument
89 return cache->miss; in log_cache_get_miss()
/Zephyr-latest/tests/subsys/logging/log_cache/src/
Dmain.c61 static void cache_get(struct log_cache *cache, uintptr_t id, in cache_get() argument
64 uint32_t hit = log_cache_get_hit(cache); in cache_get()
65 uint32_t miss = log_cache_get_miss(cache); in cache_get()
68 res = log_cache_get(cache, id, buf); in cache_get()
71 zassert_equal(hit + 1, log_cache_get_hit(cache), "line %u\n", line); in cache_get()
72 zassert_equal(miss, log_cache_get_miss(cache), "line %u\n", line); in cache_get()
74 zassert_equal(hit, log_cache_get_hit(cache), "line %u\n", line); in cache_get()
75 zassert_equal(miss + 1, log_cache_get_miss(cache), "line %u\n", line); in cache_get()
91 struct log_cache cache; in ZTEST() local
105 err = log_cache_init(&cache, &config); in ZTEST()
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/Zephyr-latest/drivers/cache/
Dcache_nrf.c44 static inline bool is_cache_busy(NRF_CACHE_Type *cache) in is_cache_busy() argument
47 return nrf_cache_busy_check(cache); in is_cache_busy()
53 static inline void wait_for_cache(NRF_CACHE_Type *cache) in wait_for_cache() argument
55 while (is_cache_busy(cache)) { in wait_for_cache()
59 static inline int _cache_all(NRF_CACHE_Type *cache, enum k_nrf_cache_op op) in _cache_all() argument
68 wait_for_cache(cache); in _cache_all()
74 nrf_cache_task_trigger(cache, NRF_CACHE_TASK_CLEANCACHE); in _cache_all()
79 nrf_cache_task_trigger(cache, NRF_CACHE_TASK_INVALIDATECACHE); in _cache_all()
84 nrf_cache_task_trigger(cache, NRF_CACHE_TASK_FLUSHCACHE); in _cache_all()
92 wait_for_cache(cache); in _cache_all()
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DKconfig5 bool "External cache controller drivers"
8 Enable support for external cache controllers drivers
16 module-str = cache
21 source "drivers/cache/Kconfig.aspeed"
22 source "drivers/cache/Kconfig.nrf"
23 source "drivers/cache/Kconfig.andes"
DKconfig.andes6 bool "ANDES external cache driver"
19 When L2 cache is inclusive of L1, CPU only needs to perform operations
20 on L2 cache, instead of on both L1 and L2 caches.
23 int "Andes cache driver init priority"
26 This option controls the priority of the cache initialization.
/Zephyr-latest/dts/riscv/starfive/
Djh7110-visionfive-v2.dtsi38 d-cache-block-size = <64>;
39 d-cache-sets = <64>;
40 d-cache-size = <32768>;
43 i-cache-block-size = <64>;
44 i-cache-sets = <64>;
45 i-cache-size = <32768>;
49 next-level-cache = <&ccache>;
63 d-cache-block-size = <64>;
64 d-cache-sets = <64>;
65 d-cache-size = <32768>;
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Dstarfive_jh7100_beagle_v.dtsi23 d-cache-block-size = <64>;
24 d-cache-sets = <64>;
25 d-cache-size = <32768>;
29 i-cache-block-size = <64>;
30 i-cache-sets = <64>;
31 i-cache-size = <32768>;
35 next-level-cache = <&cachectrl>;
52 d-cache-block-size = <64>;
53 d-cache-sets = <64>;
54 d-cache-size = <32768>;
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/Zephyr-latest/scripts/tests/twister/
Dtest_cmakecache.py182 cache = CMakeCache.from_file('dummy/path/CMakeCache.txt')
184 assert cache.cache_file == 'dummy/path/CMakeCache.txt'
193 item = cache._entries.popitem()
204 cache = CMakeCache.from_file('dummy/path/CMakeCache.txt')
206 good_val = cache.get('DUMMY_NAME')
210 bad_val = cache.get('ANOTHER_NAME')
214 bad_val = cache.get('ANOTHER_NAME', default='No such value')
237 cache = CMakeCache.from_file('dummy/path/CMakeCache.txt')
242 res = cache.get_list('DUMMY_NAME') if \
243 correct_get else cache.get_list('ANOTHER_NAME')
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/Zephyr-latest/tests/cmake/zephyr_get/
DCMakeLists.txt100 set(VARIABLE "cmake cache" CACHE INTERNAL "")
103 # CMake cache value has the highest precedence.
105 assert_equal(VARIABLE "cmake cache")
135 set(TESTCASE_VARIABLE "cmake cache" CACHE INTERNAL "")
140 IMAGE no_sysbuild "cmake cache"
189 set(VARIABLE "cmake cache" CACHE INTERNAL "")
193 assert_equal(VARIABLE "cmake cache;environment;local")
204 set(VARIABLE "cmake cache" CACHE INTERNAL "")
208 assert_equal(VARIABLE "cmake cache;local")
250 set(TESTCASE_VARIABLE "cmake cache" CACHE INTERNAL "")
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/Zephyr-latest/doc/hardware/cache/
Dindex.rst6 This is a high-level guide to Zephyr's cache interface and Kconfig options related to
7 cache controllers. See :ref:`cache_api` for API reference material.
9 Zephyr has different Kconfig options to control how the cache controller is
15 instruction cache. The cache controller can be in the core or can be an
16 external cache controller for which a driver is provided.
19 should be set whether we plan to support and use the cache control in Zephyr
23 options must be selected when support for data or instruction cache is
27 All the code paths related to cache control must be conditionally enabled
28 depending on these symbols. When the symbol is set the cache is considered
32 For example a platform using the data cache can enable the
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Dguide.rst6 This section discusses the basics of cache coherency and under what situations a
10 data cache though there is typically also an instruction cache for systems with
11 cache support.
20 While cache coherence can be a concern for data shared between SMP cores, Zephyr
22 cores. Most applications will only need to use the cache APIs for interaction
24 different OS image. For more information on cache coherence between SMP cores,
28 cache coherency needs to be considered. Typically processor caches exist as
31 processor's cache, resulting in what appears to be corrupt data. If you are
32 moving data using DMA and the processor doesn't see the data you expect, cache
37 this defeats the purpose of having a hardware cache in the first place and
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/Zephyr-latest/soc/espressif/esp32s3/
DKconfig20 prompt "Instruction cache size"
23 Instruction cache size to be set on application startup.
24 If you use 16KB instruction cache rather than 32KB instruction cache,
39 prompt "Instruction cache associated ways"
42 Instruction cache associated ways to be set on application startup.
56 prompt "Instruction cache line size"
59 Instruction cache line size to be set on application startup.
74 bool "Define instruction cache wrap mode"
76 If enabled, instruction cache will use wrap mode to read spi flash or spi ram.
81 prompt "Data cache size"
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/Zephyr-latest/cmake/modules/
Duser_cache.cmake5 # Configure user cache directory.
7 # The user cache can be used for caching of data that should be persistent
11 # Only data that can be safely re-generated should be placed in this cache.
13 # Zephyr build system uses this user cache to store Zephyr compiler check
20 # - USER_CACHE_DIR: User cache directory in use.
33 set(env_suffix_LOCALAPPDATA .cache)
36 # On macOS, ~/Library/Caches is the preferred cache directory.
39 set(env_suffix_HOME .cache)
51 # that is defined and defaulting to $HOME/.cache otherwise.
83 # Zephyr's cache files go in the "zephyr" subdirectory of the
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/Zephyr-latest/soc/espressif/esp32s2/
DKconfig20 prompt "Instruction cache line size"
32 prompt "Instruction cache size"
36 bool "8KB instruction cache size"
39 bool "16KB instruction cache size"
44 prompt "Data cache size"
47 Data cache size to be set on application startup.
59 prompt "Data cache line size"
/Zephyr-latest/subsys/net/l2/ieee802154/
Dieee802154_6lo_fragment.c48 static struct frag_cache cache[REASS_CACHE_SIZE]; variable
264 if (!(cache[i].size == size && cache[i].tag == tag)) { in clear_reass_cache()
268 if (cache[i].pkt) { in clear_reass_cache()
269 net_pkt_unref(cache[i].pkt); in clear_reass_cache()
272 cache[i].pkt = NULL; in clear_reass_cache()
273 cache[i].size = 0U; in clear_reass_cache()
274 cache[i].tag = 0U; in clear_reass_cache()
275 cache[i].used = false; in clear_reass_cache()
276 k_work_cancel_delayable(&cache[i].timer); in clear_reass_cache()
309 if (cache[i].used) { in set_reass_cache()
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/Zephyr-latest/doc/_extensions/zephyr/
Ddoxybridge.py119 cache = {}
132 cache.setdefault(kind, {})[name] = id
138 cache.setdefault("enumerator", {})[enumname] = enumid
140 return cache
144 cache = {}
149 cache.setdefault(kind, {}).update(data)
151 return cache
156 cache = {}
172 cache.setdefault(kind, {})[name] = id
176 cache.setdefault(kind, {}).update(data)
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/Zephyr-latest/arch/posix/core/
Dswap.c46 _kernel.ready_q.cache->callee_saved.thread_status; in arch_swap()
53 arch_current_thread_set(_kernel.ready_q.cache); in arch_swap()
91 _kernel.ready_q.cache->callee_saved.thread_status; in arch_switch_to_main_thread()
97 arch_current_thread_set(_kernel.ready_q.cache); in arch_switch_to_main_thread()
/Zephyr-latest/dts/riscv/andes/
Dandes_v5_ae350.dtsi26 i-cache-line-size = <32>;
27 d-cache-line-size = <32>;
43 i-cache-line-size = <32>;
44 d-cache-line-size = <32>;
60 i-cache-line-size = <32>;
61 d-cache-line-size = <32>;
77 i-cache-line-size = <32>;
78 d-cache-line-size = <32>;
94 i-cache-line-size = <32>;
95 d-cache-line-size = <32>;
[all …]
/Zephyr-latest/subsys/fs/zms/
DKconfig16 bool "ZMS lookup cache"
18 Enable ZMS cache to reduce the ZMS data lookup time.
19 Each cache entry holds an address of the most recent allocation
20 table entry (ATE) for all ZMS IDs that fall into that cache position.
23 int "ZMS Storage lookup cache size"
28 Number of entries in ZMS lookup cache.
30 Every additional entry in cache will add 8 bytes in RAM
/Zephyr-latest/subsys/fs/nvs/
DKconfig17 bool "Non-volatile Storage lookup cache"
19 Enable Non-volatile Storage cache, used to reduce the NVS data lookup
20 time. Each cache entry holds an address of the most recent allocation
21 table entry (ATE) for all NVS IDs that fall into that cache position.
24 int "Non-volatile Storage lookup cache size"
29 Number of entries in Non-volatile Storage lookup cache.
/Zephyr-latest/boards/snps/hsdk/support/
Dopenocd.cfg65 # Enable L2 cache support for core 2.
66 $_TARGETNAME2 arc cache l2 auto 1
80 # Enable L2 cache support for core 3.
81 $_TARGETNAME3 arc cache l2 auto 1
96 # Enable L2 cache support for core 4.
97 $_TARGETNAME4 arc cache l2 auto 1
111 # Enable L2 cache support for core 1.
112 $_TARGETNAME1 arc cache l2 auto 1
/Zephyr-latest/boards/snps/hsdk4xd/support/
Dopenocd.cfg65 # Enable L2 cache support for core 2.
66 $_TARGETNAME2 arc cache l2 auto 1
80 # Enable L2 cache support for core 3.
81 $_TARGETNAME3 arc cache l2 auto 1
96 # Enable L2 cache support for core 4.
97 $_TARGETNAME4 arc cache l2 auto 1
111 # Enable L2 cache support for core 1.
112 $_TARGETNAME1 arc cache l2 auto 1

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