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Searched refs:bclk_rate (Results 1 – 7 of 7) sorted by relevance

/Zephyr-latest/drivers/dai/nxp/esai/
Desai.c33 uint32_t bclk_rate, bool variable_hclk, in esai_get_clock_rate_config() argument
45 if (!extal_rate || !hclk_rate || !bclk_rate) { in esai_get_clock_rate_config()
55 if (bclk_rate > extal_rate) { in esai_get_clock_rate_config()
60 if (DIV_ROUND_UP(extal_rate, bclk_rate) > 2 * 8 * 256 * 16) { in esai_get_clock_rate_config()
62 bclk_rate, extal_rate); in esai_get_clock_rate_config()
67 if (DIV_ROUND_UP(extal_rate / 2, bclk_rate) == 1) { in esai_get_clock_rate_config()
126 hclk_div_ratio = DIV_ROUND_UP(extal_rate, bclk_rate); in esai_get_clock_rate_config()
132 hclk_div_ratio = DIV_ROUND_UP(extal_rate, bclk_rate); in esai_get_clock_rate_config()
143 hclk_div_ratio = DIV_ROUND_UP(extal_rate / i, bclk_rate); in esai_get_clock_rate_config()
144 bclk_div_ratio = DIV_ROUND_UP(extal_rate / hclk_div_ratio, bclk_rate); in esai_get_clock_rate_config()
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Desai.h198 uint32_t bclk_rate; member
/Zephyr-latest/drivers/dai/intel/ssp/
Ddai-params-intel-ipc3.h108 uint32_t bclk_rate; /* bclk frequency in Hz */ member
Dssp.c664 static int dai_ssp_mn_set_bclk(struct dai_intel_ssp *dp, uint32_t dai_index, uint32_t bclk_rate, in dai_ssp_mn_set_bclk() argument
680 if (dai_ssp_check_bclk_xtal_source(bclk_rate, mn_in_use, out_scr_div)) { in dai_ssp_mn_set_bclk()
689 ret = dai_ssp_setup_current_bclk_mn_source(dp, bclk_rate, out_scr_div, &m, &n); in dai_ssp_mn_set_bclk()
691 ret = dai_ssp_setup_initial_bclk_mn_source(dp, bclk_rate, out_scr_div, &m, &n); in dai_ssp_mn_set_bclk()
697 LOG_INF("bclk_rate %d, *out_scr_div %d, m %d, n %d", bclk_rate, *out_scr_div, m, n); in dai_ssp_mn_set_bclk()
1176 ret = dai_ssp_mn_set_bclk(dp, dp->dai_index, ssp_plat_data->params.bclk_rate, in dai_ssp_bclk_prepare_enable()
1180 ssp_plat_data->params.bclk_rate, dp->dai_index); in dai_ssp_bclk_prepare_enable()
1184 if (ft[DAI_INTEL_SSP_DEFAULT_IDX].freq % ssp_plat_data->params.bclk_rate != 0) { in dai_ssp_bclk_prepare_enable()
1186 ssp_plat_data->params.bclk_rate, dp->dai_index); in dai_ssp_bclk_prepare_enable()
1191 mdiv = ft[DAI_INTEL_SSP_DEFAULT_IDX].freq / ssp_plat_data->params.bclk_rate; in dai_ssp_bclk_prepare_enable()
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/Zephyr-latest/tests/boards/intel_adsp/ssp/src/
Dmain.c27 uint32_t bclk_rate; member
371 ssp_config.bclk_rate = 3072000; in ZTEST()
/Zephyr-latest/drivers/dai/nxp/sai/
Dsai.c196 bespoke->mclk_rate == bespoke->bclk_rate) { in sai_config_set_err_051421()
246 if (bespoke->bclk_rate != in sai_config_set()
248 LOG_ERR("bad BCLK value: %d", bespoke->bclk_rate); in sai_config_set()
Dsai.h295 uint32_t bclk_rate; member