664 static int dai_ssp_mn_set_bclk(struct dai_intel_ssp *dp, uint32_t dai_index, uint32_t bclk_rate,  in dai_ssp_mn_set_bclk()  argument
680 	if (dai_ssp_check_bclk_xtal_source(bclk_rate, mn_in_use, out_scr_div)) {  in dai_ssp_mn_set_bclk()
689 		ret = dai_ssp_setup_current_bclk_mn_source(dp, bclk_rate, out_scr_div, &m, &n);  in dai_ssp_mn_set_bclk()
691 		ret = dai_ssp_setup_initial_bclk_mn_source(dp, bclk_rate, out_scr_div, &m, &n);  in dai_ssp_mn_set_bclk()
697 		LOG_INF("bclk_rate %d, *out_scr_div %d, m %d, n %d", bclk_rate, *out_scr_div, m, n);  in dai_ssp_mn_set_bclk()
1176 	ret = dai_ssp_mn_set_bclk(dp, dp->dai_index, ssp_plat_data->params.bclk_rate,  in dai_ssp_bclk_prepare_enable()
1180 			ssp_plat_data->params.bclk_rate, dp->dai_index);  in dai_ssp_bclk_prepare_enable()
1184 	if (ft[DAI_INTEL_SSP_DEFAULT_IDX].freq % ssp_plat_data->params.bclk_rate != 0) {  in dai_ssp_bclk_prepare_enable()
1186 			ssp_plat_data->params.bclk_rate, dp->dai_index);  in dai_ssp_bclk_prepare_enable()
1191 	mdiv = ft[DAI_INTEL_SSP_DEFAULT_IDX].freq / ssp_plat_data->params.bclk_rate;  in dai_ssp_bclk_prepare_enable()
1460 	if (!ssp_plat_data->params.bclk_rate ||  in dai_ssp_set_config_tplg()
1461 		ssp_plat_data->params.bclk_rate > ssp_plat_data->params.mclk_rate) {  in dai_ssp_set_config_tplg()
1462 		LOG_ERR("BCLK %d Hz = 0 or > MCLK %d Hz", ssp_plat_data->params.bclk_rate,  in dai_ssp_set_config_tplg()
1469 	if (ssp_plat_data->params.bclk_rate % ssp_plat_data->params.fsync_rate) {  in dai_ssp_set_config_tplg()
1470 		LOG_ERR("BCLK %d is not divisible by rate %d", ssp_plat_data->params.bclk_rate,  in dai_ssp_set_config_tplg()
1477 	bdiv = ssp_plat_data->params.bclk_rate / ssp_plat_data->params.fsync_rate;  in dai_ssp_set_config_tplg()