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Searched refs:base_addr (Results 1 – 25 of 51) sorted by relevance

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/Zephyr-latest/drivers/gpio/
Dgpio_dw.c38 static inline uint32_t dw_read(uint32_t base_addr, uint32_t offset) in dw_read() argument
40 return sys_in32(base_addr + offset); in dw_read()
43 static inline void dw_write(uint32_t base_addr, uint32_t offset, in dw_write() argument
46 sys_out32(val, base_addr + offset); in dw_write()
49 static void dw_set_bit(uint32_t base_addr, uint32_t offset, in dw_set_bit() argument
53 sys_io_clear_bit(base_addr + offset, bit); in dw_set_bit()
55 sys_io_set_bit(base_addr + offset, bit); in dw_set_bit()
59 static inline uint32_t dw_read(uint32_t base_addr, uint32_t offset) in dw_read() argument
61 return sys_read32(base_addr + offset); in dw_read()
64 static inline void dw_write(uint32_t base_addr, uint32_t offset, in dw_write() argument
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Dgpio_creg_gpio.c29 uint32_t base_addr; member
47 uint32_t in = sys_read32(drv_data->base_addr); in port_get()
77 sys_write32(out, drv_data->base_addr); in port_write()
171 .base_addr = DT_INST_REG_ADDR(0),
Dgpio_efinix_sapphire.c39 uint32_t base_addr; member
53 #define GPIO_OUTPUT_ADDR config->base_addr + BSP_GPIO_OUTPUT
59 #define GPIO_OUTPUT_ENABLE_ADDR config->base_addr + BSP_GPIO_OUTPUT_ENABLE in cfg_output_enable_bit()
220 .base_addr = DT_INST_REG_ADDR(n), \
Dgpio_dw.h31 uint32_t base_addr; member
/Zephyr-latest/drivers/ethernet/
Dphy_xlnx_gem.c37 uint32_t base_addr, uint8_t phy_addr, in phy_xlnx_gem_mdio_read() argument
56 reg_val = sys_read32(base_addr + ETH_XLNX_GEM_NWSR_OFFSET); in phy_xlnx_gem_mdio_read()
61 base_addr, phy_addr, reg_addr); in phy_xlnx_gem_mdio_read()
78 sys_write32(reg_val, base_addr + ETH_XLNX_GEM_PHY_MAINTENANCE_OFFSET); in phy_xlnx_gem_mdio_read()
89 reg_val = sys_read32(base_addr + ETH_XLNX_GEM_NWSR_OFFSET); in phy_xlnx_gem_mdio_read()
94 base_addr, phy_addr, reg_addr); in phy_xlnx_gem_mdio_read()
102 reg_val = sys_read32(base_addr + ETH_XLNX_GEM_PHY_MAINTENANCE_OFFSET); in phy_xlnx_gem_mdio_read()
116 uint32_t base_addr, uint8_t phy_addr, in phy_xlnx_gem_mdio_write() argument
135 reg_val = sys_read32(base_addr + ETH_XLNX_GEM_NWSR_OFFSET); in phy_xlnx_gem_mdio_write()
140 base_addr, phy_addr, reg_addr); in phy_xlnx_gem_mdio_write()
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Deth_cyclonev.c135 sys_write32(tmpreg, EMAC_GMAC_MAC_ADDR_HIGH_ADDR(p->base_addr, n)); in eth_cyclonev_set_mac_addr()
142 sys_write32(tmpreg, EMAC_GMAC_MAC_ADDR_LOW_ADDR(p->base_addr, n)); in eth_cyclonev_set_mac_addr()
158 return EMAC_DMA_MODE_SWR_GET(sys_read32(EMAC_DMAGRP_BUS_MODE_ADDR(p->base_addr))); in eth_cyclonev_get_software_reset_status()
180 sys_set_bits(EMAC_DMAGRP_BUS_MODE_ADDR(p->base_addr), EMAC_DMA_MODE_SWR_SET_MSK); in eth_cyclonev_software_reset()
230 EMAC_DMA_RX_DESC_LIST_ADDR(p->base_addr)); in eth_cyclonev_setup_rxdesc()
266 EMAC_DMA_TX_DESC_LIST_ADDR(p->base_addr)); in eth_cyclonev_setup_txdesc()
332 reg_val = sys_read32(EMAC_GMACGRP_MAC_FRAME_FILTER_ADDR(p->base_addr)); in eth_cyclonev_set_config()
335 sys_set_bits(EMAC_GMACGRP_MAC_FRAME_FILTER_ADDR(p->base_addr), in eth_cyclonev_set_config()
340 sys_clear_bits(EMAC_GMACGRP_MAC_FRAME_FILTER_ADDR(p->base_addr), in eth_cyclonev_set_config()
482 p->base_addr), in eth_cyclonev_send()
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Deth_xlnx_gem.c201 reg_val = sys_read32(dev_conf->base_addr + in DT_INST_FOREACH_STATUS_OKAY()
204 sys_write32(reg_val, dev_conf->base_addr + in DT_INST_FOREACH_STATUS_OKAY()
276 reg_val = sys_read32(dev_conf->base_addr + ETH_XLNX_GEM_ISR_OFFSET); in eth_xlnx_gem_isr()
298 dev_conf->base_addr + ETH_XLNX_GEM_IDR_OFFSET); in eth_xlnx_gem_isr()
300 dev_conf->base_addr + ETH_XLNX_GEM_ISR_OFFSET); in eth_xlnx_gem_isr()
309 dev_conf->base_addr + ETH_XLNX_GEM_IDR_OFFSET); in eth_xlnx_gem_isr()
311 dev_conf->base_addr + ETH_XLNX_GEM_ISR_OFFSET); in eth_xlnx_gem_isr()
330 dev_conf->base_addr + ETH_XLNX_GEM_ISR_OFFSET); in eth_xlnx_gem_isr()
401 dev_conf->base_addr + ETH_XLNX_GEM_IDR_OFFSET); in eth_xlnx_gem_send()
414 dev_conf->base_addr + ETH_XLNX_GEM_IER_OFFSET); in eth_xlnx_gem_send()
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Dphy_cyclonev.c122 sys_write32(phy_value & 0xffff, EMAC_GMAC_GMII_DATA_ADDR(p->base_addr)); in alt_eth_phy_write_register()
124 sys_write32(tmpreg & 0xffff, EMAC_GMAC_GMII_ADDR_ADDR(p->base_addr)); in alt_eth_phy_write_register()
130 tmpreg = sys_read32(EMAC_GMAC_GMII_ADDR_ADDR(p->base_addr)); in alt_eth_phy_write_register()
169 sys_write32(tmpreg & 0xffff, EMAC_GMAC_GMII_ADDR_ADDR(p->base_addr)); in alt_eth_phy_read_register()
174 tmpreg = sys_read32(EMAC_GMAC_GMII_ADDR_ADDR(p->base_addr)); in alt_eth_phy_read_register()
183 *rdval = sys_read32(EMAC_GMAC_GMII_DATA_ADDR(p->base_addr)); in alt_eth_phy_read_register()
/Zephyr-latest/include/zephyr/drivers/mm/
Drat.h18 #define RAT_CTRL(base_addr, i) (base_addr + 0x20 + 0x10 * (i)) argument
19 #define RAT_BASE(base_addr, i) (base_addr + 0x24 + 0x10 * (i)) argument
20 #define RAT_TRANS_L(base_addr, i) (base_addr + 0x28 + 0x10 * (i)) argument
21 #define RAT_TRANS_H(base_addr, i) (base_addr + 0x2C + 0x10 * (i)) argument
/Zephyr-latest/drivers/bbram/
Dbbram_it8xxx2.c45 bytecpy(data, ((uint8_t *)config->base_addr + offset), size); in bbram_it8xxx2_read()
58 bytecpy(((uint8_t *)config->base_addr + offset), data, size); in bbram_it8xxx2_write()
79 uint8_t *base_addr = (uint8_t *)config->base_addr; in bbram_it8xxx2_init() local
80 uint8_t *bram_valid_flag0 = base_addr + BRAM_IDX_VALID_FLAGS0; in bbram_it8xxx2_init()
81 uint8_t *bram_valid_flag1 = base_addr + BRAM_IDX_VALID_FLAGS1; in bbram_it8xxx2_init()
82 uint8_t *bram_valid_flag2 = base_addr + BRAM_IDX_VALID_FLAGS2; in bbram_it8xxx2_init()
83 uint8_t *bram_valid_flag3 = base_addr + BRAM_IDX_VALID_FLAGS3; in bbram_it8xxx2_init()
95 *(base_addr + i) = 0; in bbram_it8xxx2_init()
Dit8xxx2.h16 uintptr_t base_addr; member
25 .base_addr = (uintptr_t)bbram_it8xxx2_emul_buffer_##inst, \
31 .base_addr = DT_INST_REG_ADDR(inst), \
Dnpcx.h16 uintptr_t base_addr; member
28 .base_addr = (uintptr_t)bbram_npcx_emul_buffer_##inst, \
35 .base_addr = DT_INST_REG_ADDR_BY_NAME(inst, memory), \
Dbbram_it8xxx2_emul.c31 bytecpy(((uint8_t *)config->base_addr + offset), buffer, count); in it8xxx2_emul_backend_set_data()
44 bytecpy(buffer, ((uint8_t *)config->base_addr + offset), count); in it8xxx2_emul_backend_get_data()
Dbbram_npcx_emul.c31 bytecpy(((uint8_t *)config->base_addr + offset), buffer, count); in npcx_emul_backend_set_data()
44 bytecpy(buffer, ((uint8_t *)config->base_addr + offset), count); in npcx_emul_backend_get_data()
Dbbram_stm32.c29 #define STM32_BKP_REG(i) (((volatile uint32_t *)config->base_addr)[(i)])
35 uintptr_t base_addr; member
118 .base_addr = DT_REG_ADDR(DT_INST_PARENT(inst)) + STM32_BKP_REG_OFFSET, \
/Zephyr-latest/tests/drivers/syscon/src/
Dmain.c39 uintptr_t base_addr; in ZTEST() local
42 zassert_ok(syscon_get_base(dev, &base_addr)); in ZTEST()
44 ((uint8_t *)base_addr)[i] = i; in ZTEST()
53 uintptr_t base_addr; in ZTEST() local
55 zassert_ok(syscon_get_base(dev, &base_addr)); in ZTEST()
58 zassert_equal(((uint8_t *)base_addr)[i], i); in ZTEST()
/Zephyr-latest/drivers/interrupt_controller/
Dintc_dw.c43 (struct dw_ictl_registers *)config->base_addr; in dw_ictl_initialize()
56 (struct dw_ictl_registers *)config->base_addr; in dw_ictl_isr()
72 (struct dw_ictl_registers *)config->base_addr; in dw_ictl_intr_enable()
86 (struct dw_ictl_registers *)config->base_addr; in dw_ictl_intr_disable()
99 (struct dw_ictl_registers *)config->base_addr; in dw_ictl_intr_get_state()
118 (struct dw_ictl_registers *)config->base_addr; in dw_ictl_intr_get_line_state()
136 .base_addr = DT_INST_REG_ADDR(0),
Dintc_cavs.c32 return UINT_TO_POINTER(context->base_addr + in get_base_address()
35 return UINT_TO_POINTER(context->base_addr); in get_base_address()
141 .base_addr = DT_INST_REG_ADDR(n), \
Dintc_cavs.h25 uint32_t base_addr; member
/Zephyr-latest/soc/intel/intel_adsp/common/
Dmem_window.c29 sys_write32(config->size | 0x7, DMWLO(config->base_addr)); in mem_win_init()
32 DMWBA(config->base_addr)); in mem_win_init()
34 sys_write32((config->mem_base | ADSP_DMWBA_ENABLE), DMWBA(config->base_addr)); in mem_win_init()
50 .base_addr = DT_REG_ADDR(MEM_WINDOW_NODE(n)), \
/Zephyr-latest/drivers/peci/
Dpeci_ite_it8xxx2.c95 uintptr_t base_addr; member
109 .base_addr = DT_INST_REG_ADDR(0),
139 (struct peci_it8xxx2_regs *)config->base_addr; in peci_it8xxx2_check_host_finish()
161 (struct peci_it8xxx2_regs *)config->base_addr; in peci_it8xxx2_configure()
199 (struct peci_it8xxx2_regs *)config->base_addr; in peci_it8xxx2_enable()
210 (struct peci_it8xxx2_regs *)config->base_addr; in peci_it8xxx2_disable()
220 (struct peci_it8xxx2_regs *)config->base_addr; in peci_it8xxx2_rst_module()
244 (struct peci_it8xxx2_regs *)config->base_addr; in peci_it8xxx2_transfer()
316 (struct peci_it8xxx2_regs *)config->base_addr; in peci_it8xxx2_init()
/Zephyr-latest/drivers/misc/ethos_u/
Dethos_u.c109 void *base_addr; member
135 config->base_addr, config->secure_enable, config->privilege_enable); in ethosu_zephyr_init()
142 if (ethosu_init(drv, config->base_addr, NULL, 0, config->secure_enable, in ethosu_zephyr_init()
164 .base_addr = (void *)DT_INST_REG_ADDR(n), \
/Zephyr-latest/drivers/flash/
Dflash_ifx_cat1.c24 uint32_t base_addr; member
57 uint32_t read_offset = dev_config->base_addr + offset; in ifx_cat1_flash_read()
80 uint32_t write_offset = dev_config->base_addr + (uint32_t)offset; in ifx_cat1_flash_write()
118 uint32_t erase_offset = config->base_addr + (uint32_t)offset; in ifx_cat1_flash_erase()
200 .base_addr = DT_REG_ADDR(SOC_NV_FLASH_NODE),
/Zephyr-latest/samples/drivers/led/xec/src/
Dmain.c21 uint32_t base_addr; member
25 { .dev = DEVICE_DT_GET(node_id), .base_addr = (uint32_t)DT_REG_ADDR(node_id) },
70 uint32_t base = led_dev_table[n].base_addr; in led_test()
/Zephyr-latest/drivers/i2c/
Di2c_mchp_xec_v2.c88 uint32_t base_addr; member
147 struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr; in i2c_ctl_wr()
164 struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr; in wait_bus_free()
207 struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr; in get_lines()
222 struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr; in i2c_xec_reset_config()
314 struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr; in i2c_xec_recover_bus()
434 struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr; in wait_pin()
475 struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr; in gen_start()
499 struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr; in gen_stop()
515 struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr; in do_stop()
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