201 		reg_val  = sys_read32(dev_conf->base_addr +  in DT_INST_FOREACH_STATUS_OKAY()
204 		sys_write32(reg_val, dev_conf->base_addr +  in DT_INST_FOREACH_STATUS_OKAY()
276 	reg_val = sys_read32(dev_conf->base_addr + ETH_XLNX_GEM_ISR_OFFSET);  in eth_xlnx_gem_isr()
298 			    dev_conf->base_addr + ETH_XLNX_GEM_IDR_OFFSET);  in eth_xlnx_gem_isr()
300 			    dev_conf->base_addr + ETH_XLNX_GEM_ISR_OFFSET);  in eth_xlnx_gem_isr()
309 			    dev_conf->base_addr + ETH_XLNX_GEM_IDR_OFFSET);  in eth_xlnx_gem_isr()
311 			    dev_conf->base_addr + ETH_XLNX_GEM_ISR_OFFSET);  in eth_xlnx_gem_isr()
330 		    dev_conf->base_addr + ETH_XLNX_GEM_ISR_OFFSET);  in eth_xlnx_gem_isr()
401 			    dev_conf->base_addr + ETH_XLNX_GEM_IDR_OFFSET);  in eth_xlnx_gem_send()
414 				    dev_conf->base_addr + ETH_XLNX_GEM_IER_OFFSET);  in eth_xlnx_gem_send()
433 			    dev_conf->base_addr + ETH_XLNX_GEM_IER_OFFSET);  in eth_xlnx_gem_send()
491 	reg_val  = sys_read32(dev_conf->base_addr + ETH_XLNX_GEM_NWCTRL_OFFSET);  in eth_xlnx_gem_send()
493 	sys_write32(reg_val, dev_conf->base_addr + ETH_XLNX_GEM_NWCTRL_OFFSET);  in eth_xlnx_gem_send()
537 		    dev_conf->base_addr + ETH_XLNX_GEM_IDR_OFFSET);  in eth_xlnx_gem_start_device()
539 		    dev_conf->base_addr + ETH_XLNX_GEM_ISR_OFFSET);  in eth_xlnx_gem_start_device()
542 	sys_write32(0xFFFFFFFF, dev_conf->base_addr + ETH_XLNX_GEM_TXSR_OFFSET);  in eth_xlnx_gem_start_device()
543 	sys_write32(0xFFFFFFFF, dev_conf->base_addr + ETH_XLNX_GEM_RXSR_OFFSET);  in eth_xlnx_gem_start_device()
546 	reg_val  = sys_read32(dev_conf->base_addr + ETH_XLNX_GEM_NWCTRL_OFFSET);  in eth_xlnx_gem_start_device()
548 	sys_write32(reg_val, dev_conf->base_addr + ETH_XLNX_GEM_NWCTRL_OFFSET);  in eth_xlnx_gem_start_device()
552 		    dev_conf->base_addr + ETH_XLNX_GEM_IER_OFFSET);  in eth_xlnx_gem_start_device()
590 	reg_val  = sys_read32(dev_conf->base_addr + ETH_XLNX_GEM_NWCTRL_OFFSET);  in eth_xlnx_gem_stop_device()
592 	sys_write32(reg_val, dev_conf->base_addr + ETH_XLNX_GEM_NWCTRL_OFFSET);  in eth_xlnx_gem_stop_device()
596 		    dev_conf->base_addr + ETH_XLNX_GEM_IDR_OFFSET);  in eth_xlnx_gem_stop_device()
598 		    dev_conf->base_addr + ETH_XLNX_GEM_ISR_OFFSET);  in eth_xlnx_gem_stop_device()
601 	sys_write32(0xFFFFFFFF, dev_conf->base_addr + ETH_XLNX_GEM_TXSR_OFFSET);  in eth_xlnx_gem_stop_device()
602 	sys_write32(0xFFFFFFFF, dev_conf->base_addr + ETH_XLNX_GEM_RXSR_OFFSET);  in eth_xlnx_gem_stop_device()
747 		    dev_conf->base_addr + ETH_XLNX_GEM_NWCTRL_OFFSET);  in eth_xlnx_gem_reset_hw()
751 		    dev_conf->base_addr + ETH_XLNX_GEM_NWCTRL_OFFSET);  in eth_xlnx_gem_reset_hw()
755 		    dev_conf->base_addr + ETH_XLNX_GEM_TXSR_OFFSET);  in eth_xlnx_gem_reset_hw()
757 		    dev_conf->base_addr + ETH_XLNX_GEM_RXSR_OFFSET);  in eth_xlnx_gem_reset_hw()
761 		    dev_conf->base_addr + ETH_XLNX_GEM_IDR_OFFSET);  in eth_xlnx_gem_reset_hw()
765 		    dev_conf->base_addr + ETH_XLNX_GEM_RXQBASE_OFFSET);  in eth_xlnx_gem_reset_hw()
767 		    dev_conf->base_addr + ETH_XLNX_GEM_TXQBASE_OFFSET);  in eth_xlnx_gem_reset_hw()
1014 	sys_write32(reg_val, dev_conf->base_addr + ETH_XLNX_GEM_NWCFG_OFFSET);  in eth_xlnx_gem_set_initial_nwcfg()
1034 	reg_val  = sys_read32(dev_conf->base_addr + ETH_XLNX_GEM_NWCFG_OFFSET);  in eth_xlnx_gem_set_nwcfg_link_speed()
1045 	sys_write32(reg_val, dev_conf->base_addr + ETH_XLNX_GEM_NWCFG_OFFSET);  in eth_xlnx_gem_set_nwcfg_link_speed()
1073 	sys_write32(regval_bot, dev_conf->base_addr + ETH_XLNX_GEM_LADDR1L_OFFSET);  in eth_xlnx_gem_set_mac_address()
1074 	sys_write32(regval_top, dev_conf->base_addr + ETH_XLNX_GEM_LADDR1H_OFFSET);  in eth_xlnx_gem_set_mac_address()
1149 	sys_write32(reg_val, dev_conf->base_addr + ETH_XLNX_GEM_DMACR_OFFSET);  in eth_xlnx_gem_set_initial_dmacr()
1382 		    dev_conf->base_addr + ETH_XLNX_GEM_RXQBASE_OFFSET);  in eth_xlnx_gem_configure_buffers()
1384 		    dev_conf->base_addr + ETH_XLNX_GEM_TXQBASE_OFFSET);  in eth_xlnx_gem_configure_buffers()
1439 	reg_val_rxsr = sys_read32(dev_conf->base_addr + ETH_XLNX_GEM_RXSR_OFFSET);  in eth_xlnx_gem_handle_rx_pending()
1561 	sys_write32(0xFFFFFFFF, dev_conf->base_addr + ETH_XLNX_GEM_RXSR_OFFSET);  in eth_xlnx_gem_handle_rx_pending()
1564 		    dev_conf->base_addr + ETH_XLNX_GEM_IER_OFFSET);  in eth_xlnx_gem_handle_rx_pending()
1616 	reg_val_txsr = sys_read32(dev_conf->base_addr + ETH_XLNX_GEM_TXSR_OFFSET);  in eth_xlnx_gem_handle_tx_done()
1676 	sys_write32(0xFFFFFFFF, dev_conf->base_addr + ETH_XLNX_GEM_TXSR_OFFSET);  in eth_xlnx_gem_handle_tx_done()
1680 		    dev_conf->base_addr + ETH_XLNX_GEM_IER_OFFSET);  in eth_xlnx_gem_handle_tx_done()