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Searched refs:bank (Results 1 – 25 of 94) sorted by relevance

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/Zephyr-latest/drivers/mm/
Dmm_drv_bank.c21 void sys_mm_drv_bank_init(struct sys_mm_drv_bank *bank, uint32_t bank_pages) in sys_mm_drv_bank_init() argument
23 bank->unmapped_pages = 0; in sys_mm_drv_bank_init()
24 bank->mapped_pages = bank_pages; in sys_mm_drv_bank_init()
25 bank->max_mapped_pages = bank_pages; in sys_mm_drv_bank_init()
28 uint32_t sys_mm_drv_bank_page_mapped(struct sys_mm_drv_bank *bank) in sys_mm_drv_bank_page_mapped() argument
30 bank->unmapped_pages--; in sys_mm_drv_bank_page_mapped()
31 bank->mapped_pages++; in sys_mm_drv_bank_page_mapped()
32 if (bank->mapped_pages > bank->max_mapped_pages) { in sys_mm_drv_bank_page_mapped()
33 bank->max_mapped_pages = bank->mapped_pages; in sys_mm_drv_bank_page_mapped()
35 return bank->mapped_pages; in sys_mm_drv_bank_page_mapped()
[all …]
/Zephyr-latest/drivers/gpio/
Dgpio_xlnx_ps.c49 uint32_t bank; in gpio_xlnx_ps_init() local
57 for (bank = 0; bank < dev_conf->num_banks; bank++) { in gpio_xlnx_ps_init()
59 dev_conf->bank_devices[bank]->data; in gpio_xlnx_ps_init()
60 __ASSERT(bank_data != NULL, "%s bank %u data unresolved", dev->name, bank); in gpio_xlnx_ps_init()
89 uint32_t bank; in gpio_xlnx_ps_isr() local
92 for (bank = 0; bank < dev_conf->num_banks; bank++) { in gpio_xlnx_ps_isr()
93 api = dev_conf->bank_devices[bank]->api; in gpio_xlnx_ps_isr()
97 int_mask = api->get_pending_int(dev_conf->bank_devices[bank]); in gpio_xlnx_ps_isr()
101 dev_conf->bank_devices[bank]->data; in gpio_xlnx_ps_isr()
103 dev_conf->bank_devices[bank], int_mask); in gpio_xlnx_ps_isr()
Dgpio_adp5585.c84 uint8_t bank = ADP5585_BANK(pin); in gpio_adp5585_config() local
109 ret = i2c_reg_update_byte_dt(&parent_cfg->i2c_bus, ADP5585_GPO_OUT_MODE_A + bank, in gpio_adp5585_config()
115 uint8_t regaddr = ADP5585_RPULL_CONFIG_A + (bank << 1); in gpio_adp5585_config()
145 if (bank == 0) { in gpio_adp5585_config()
153 ADP5585_GPO_OUT_MODE_A + bank, in gpio_adp5585_config()
166 ADP5585_GPIO_DIRECTION_A + bank, in gpio_adp5585_config()
305 uint8_t bank = ADP5585_BANK(pin); in gpio_adp5585_pin_interrupt_configure() local
312 ADP5585_GPI_INTERRUPT_EN_A + bank, BIT(bank_pin), in gpio_adp5585_pin_interrupt_configure()
317 &parent_cfg->i2c_bus, ADP5585_GPI_INT_LEVEL_A + bank, in gpio_adp5585_pin_interrupt_configure()
321 &parent_cfg->i2c_bus, ADP5585_GPI_INT_LEVEL_A + bank, in gpio_adp5585_pin_interrupt_configure()
[all …]
/Zephyr-latest/include/zephyr/drivers/mm/
Dmm_drv_bank.h65 void sys_mm_drv_bank_init(struct sys_mm_drv_bank *bank, uint32_t bank_pages);
77 uint32_t sys_mm_drv_bank_page_mapped(struct sys_mm_drv_bank *bank);
89 uint32_t sys_mm_drv_bank_page_unmapped(struct sys_mm_drv_bank *bank);
100 void sys_mm_drv_bank_stats_reset_max(struct sys_mm_drv_bank *bank);
110 void sys_mm_drv_bank_stats_get(struct sys_mm_drv_bank *bank,
/Zephyr-latest/arch/arc/core/mpu/
Darc_mpu_v6_internal.h65 static inline void _bank_select(uint32_t bank) in _bank_select() argument
70 z_arc_v2_aux_reg_write(_ARC_V2_MPU_EN, val | bank); in _bank_select()
78 uint32_t bank = index / ARC_FEATURE_MPU_BANK_SIZE; in _region_init() local
107 _bank_select(bank); in _region_init()
150 uint32_t bank = r_index / ARC_FEATURE_MPU_BANK_SIZE; in _is_enabled_region() local
153 _bank_select(bank); in _is_enabled_region()
166 uint32_t bank = r_index / ARC_FEATURE_MPU_BANK_SIZE; in _is_in_region() local
169 _bank_select(bank); in _is_in_region()
188 uint32_t bank = r_index / ARC_FEATURE_MPU_BANK_SIZE; in _is_user_accessible_region() local
191 _bank_select(bank); in _is_user_accessible_region()
/Zephyr-latest/drivers/memc/
Dmemc_sam_smc.c37 SmcCs_number *bank; in memc_smc_init() local
53 bank = &cfg->regs->SMC_CS_NUMBER[cfg->banks[i].cs]; in memc_smc_init()
55 bank->SMC_SETUP = cfg->banks[i].setup_timing; in memc_smc_init()
56 bank->SMC_PULSE = cfg->banks[i].pulse_timing; in memc_smc_init()
57 bank->SMC_CYCLE = cfg->banks[i].cycle_timing; in memc_smc_init()
58 bank->SMC_MODE = cfg->banks[i].mode; in memc_smc_init()
/Zephyr-latest/soc/snps/arc_iot/
Dsysconf.c171 void arc_iot_gpio8b_dbclk_div(uint8_t bank, uint8_t div) in arc_iot_gpio8b_dbclk_div() argument
173 if (bank == GPIO8B_BANK0) { in arc_iot_gpio8b_dbclk_div()
176 } else if (bank == GPIO8B_BANK1) { in arc_iot_gpio8b_dbclk_div()
179 } else if (bank == GPIO8B_BANK2) { in arc_iot_gpio8b_dbclk_div()
182 } else if (bank == GPIO8B_BANK3) { in arc_iot_gpio8b_dbclk_div()
188 void arc_iot_gpio4b_dbclk_div(uint8_t bank, uint8_t div) in arc_iot_gpio4b_dbclk_div() argument
190 if (bank == GPIO4B_BANK0) { in arc_iot_gpio4b_dbclk_div()
193 } else if (bank == GPIO4B_BANK1) { in arc_iot_gpio4b_dbclk_div()
196 } else if (bank == GPIO4B_BANK2) { in arc_iot_gpio4b_dbclk_div()
Dsysconf.h148 extern void arc_iot_gpio8b_dbclk_div(uint8_t bank, uint8_t div);
149 extern void arc_iot_gpio4b_dbclk_div(uint8_t bank, uint8_t div);
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-rcar-common.h25 #define IPSR(bank, shift, func) (((bank) << 10U) | ((shift) << 4U) | (func)) argument
36 #define RCAR_GP_PIN(bank, pin) (((bank) * 32U) + (pin)) argument
49 #define IPnSR(bank, reg, shift, func) \ argument
50 IPSR(((reg) << 5U) | (bank), shift, func)
/Zephyr-latest/drivers/flash/
DKconfig.renesas_ra29 bool "Dual bank mode"
31 Enable dual bank mode
Dflash_stm32h7x.c60 int bank; member
295 sector.bank = 1;
300 sector.bank = 1;
304 sector.bank = 2;
309 sector.bank = 2;
314 sector.bank = 0;
321 sector.bank = 1;
326 sector.bank = 0;
340 if (sector.bank == 0) {
403 if (sector.bank == 0) {
/Zephyr-latest/boards/st/nucleo_l053r8/support/
Dopenocd.cfg11 # Add the second flash bank.
13 flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
/Zephyr-latest/boards/st/nucleo_l073rz/support/
Dopenocd.cfg11 # Add the second flash bank.
13 flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
/Zephyr-latest/soc/nxp/lpc/lpc54xxx/
DKconfig65 SRAM2 ram bank is disabled out of reset. By default, CMSIS SystemInit
66 will enable the clock to this RAM bank. Disable this Kconfig to leave
67 this ram bank untouched out of reset.
DCMakeLists.txt17 # CMSIS SystemInit allows us to skip enabling clock to SRAM2 bank via
/Zephyr-latest/drivers/usb/device/
Dusb_dc_sam0.c296 UsbDeviceDescBank *bank; in usb_dc_release_buffers() local
302 bank = &data->descriptors[i].DeviceDescBank[j]; in usb_dc_release_buffers()
303 buf = (void *)bank->ADDR.reg; in usb_dc_release_buffers()
312 bank->ADDR.reg = (uintptr_t) NULL; in usb_dc_release_buffers()
387 UsbDeviceDescBank *bank; in usb_dc_ep_configure() local
424 bank = &desc->DeviceDescBank[1]; in usb_dc_ep_configure()
426 bank = &desc->DeviceDescBank[0]; in usb_dc_ep_configure()
429 buf = (void *)bank->ADDR.reg; in usb_dc_ep_configure()
431 if (bank->PCKSIZE.bit.SIZE != size || buf == NULL) { in usb_dc_ep_configure()
439 bank->PCKSIZE.bit.SIZE = size; in usb_dc_ep_configure()
[all …]
/Zephyr-latest/dts/arm/xilinx/
Dzynqmp.dtsi224 compatible = "xlnx,ps-gpio-bank";
233 compatible = "xlnx,ps-gpio-bank";
242 compatible = "xlnx,ps-gpio-bank";
251 compatible = "xlnx,ps-gpio-bank";
260 compatible = "xlnx,ps-gpio-bank";
269 compatible = "xlnx,ps-gpio-bank";
Dzynq7000.dtsi135 compatible = "xlnx,ps-gpio-bank";
144 compatible = "xlnx,ps-gpio-bank";
153 compatible = "xlnx,ps-gpio-bank";
162 compatible = "xlnx,ps-gpio-bank";
/Zephyr-latest/drivers/pinctrl/renesas/rcar/
Dpfc_rcar.c74 uint8_t bank = pin / 32; in pfc_rcar_set_gpsr() local
77 uint8_t bank = 0; in pfc_rcar_set_gpsr()
81 bank * sizeof(uint32_t)); in pfc_rcar_set_gpsr()
88 pfc_rcar_write(pfc_base, PFC_RCAR_GPSR + bank * sizeof(uint32_t), val); in pfc_rcar_set_gpsr()
95 uint16_t reg_offs = PFC_RCAR_IPSR + rcar_func->bank * sizeof(uint32_t); in pfc_rcar_set_ipsr()
/Zephyr-latest/boards/wch/ch32v003evt/support/
Dopenocd.cfg13 flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0
/Zephyr-latest/boards/openisa/rv32m1_vega/support/
Dopenocd_rv32m1_vega_zero_riscy.cfg46 flash bank $_CHIPNAME.flash0 rv32m1 0 0 0 0 $_TARGETNAME # For core 0
47 flash bank $_CHIPNAME.flash1 rv32m1 0x01000000 0 0 0 $_TARGETNAME # For core 1
Dopenocd_rv32m1_vega_ri5cy.cfg46 flash bank $_CHIPNAME.flash0 rv32m1 0 0 0 0 $_TARGETNAME # For core 0
47 flash bank $_CHIPNAME.flash1 rv32m1 0x01000000 0 0 0 $_TARGETNAME # For core 1
/Zephyr-latest/boards/sifive/hifive1/support/
Dopenocd.cfg16 flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
/Zephyr-latest/dts/arm/ambiq/
Dambiq_apollo4p_blue.dtsi365 compatible = "ambiq,gpio-bank";
374 compatible = "ambiq,gpio-bank";
383 compatible = "ambiq,gpio-bank";
392 compatible = "ambiq,gpio-bank";
/Zephyr-latest/drivers/sensor/tdk/icm42688/
Dicm42688_reg.h31 #define REG_BANK_OFFSET(bank) (bank << 8) argument

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