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/Zephyr-latest/drivers/adc/
DKconfig57 source "drivers/adc/Kconfig.b91"
59 source "drivers/adc/Kconfig.it8xxx2"
61 source "drivers/adc/Kconfig.mcux"
63 source "drivers/adc/Kconfig.nrfx"
65 source "drivers/adc/Kconfig.sam_afec"
67 source "drivers/adc/Kconfig.sam"
69 source "drivers/adc/Kconfig.sam0"
71 source "drivers/adc/Kconfig.stm32"
73 source "drivers/adc/Kconfig.esp32"
75 source "drivers/adc/Kconfig.xec"
[all …]
Dadc_shell.c164 struct adc_hdl *adc = get_adc(argv[-2]); in cmd_adc_ch_id() local
167 if (!device_is_ready(adc->dev)) { in cmd_adc_ch_id()
177 adc->channel_config.channel_id = (uint8_t)strtol(argv[1], NULL, 10); in cmd_adc_ch_id()
178 retval = adc_channel_setup(adc->dev, &adc->channel_config); in cmd_adc_ch_id()
187 struct adc_hdl *adc = get_adc(argv[-2]); in cmd_adc_ch_diff() local
192 if (!device_is_ready(adc->dev)) { in cmd_adc_ch_diff()
204 adc->channel_config.differential = (uint8_t)diff; in cmd_adc_ch_diff()
205 retval = adc_channel_setup(adc->dev, &adc->channel_config); in cmd_adc_ch_diff()
215 struct adc_hdl *adc = get_adc(argv[-2]); in cmd_adc_ch_neg() local
218 if (!device_is_ready(adc->dev)) { in cmd_adc_ch_neg()
[all …]
Dadc_stm32.c194 static void adc_stm32_enable_dma_support(ADC_TypeDef *adc) in adc_stm32_enable_dma_support() argument
198 LL_ADC_REG_SetDMATransfer(adc, LL_ADC_REG_DMA_TRANSFER_UNLIMITED); in adc_stm32_enable_dma_support()
203 LL_ADC_REG_SetDataTransferMode(adc, LL_ADC_REG_DMA_TRANSFER_LIMITED); in adc_stm32_enable_dma_support()
206 LL_ADC_REG_SetDMATransfer(adc, LL_ADC_REG_DMA_TRANSFER_LIMITED); in adc_stm32_enable_dma_support()
214 ADC_TypeDef *adc = config->base; in adc_stm32_dma_start() local
227 blk_cfg->source_address = (uint32_t)LL_ADC_DMA_GetRegAddr(adc, LL_ADC_DMA_REG_REGULAR_DATA); in adc_stm32_dma_start()
251 adc_stm32_enable_dma_support(adc); in adc_stm32_dma_start()
325 static int adc_stm32_enable(ADC_TypeDef *adc) in adc_stm32_enable() argument
327 if (LL_ADC_IsEnabled(adc) == 1UL) { in adc_stm32_enable()
333 LL_ADC_ClearFlag_ADRDY(adc); in adc_stm32_enable()
[all …]
Dadc_sam0.c64 static void wait_synchronization(Adc *const adc) in wait_synchronization() argument
66 while ((ADC_SYNC(adc) & ADC_SYNC_MASK) != 0) { in wait_synchronization()
119 Adc *const adc = cfg->regs; in adc_sam0_channel_setup() local
134 adc->SAMPCTRL.reg = sampctrl; in adc_sam0_channel_setup()
135 wait_synchronization(adc); in adc_sam0_channel_setup()
165 if (adc->REFCTRL.reg != refctrl) { in adc_sam0_channel_setup()
167 adc->CTRLA.bit.ENABLE = 0; in adc_sam0_channel_setup()
168 wait_synchronization(adc); in adc_sam0_channel_setup()
170 adc->REFCTRL.reg = refctrl; in adc_sam0_channel_setup()
171 wait_synchronization(adc); in adc_sam0_channel_setup()
[all …]
Dadc_sam.c70 Adc *const adc = cfg->regs; in adc_sam_channel_setup() local
99 adc->ADC_ACR |= ADC_ACR_TSON; in adc_sam_channel_setup()
104 adc->ADC_COR |= (ADC_COR_DIFF0 | ADC_COR_DIFF1) << (channel_id * 2U); in adc_sam_channel_setup()
106 adc->ADC_COR &= ~((ADC_COR_DIFF0 | ADC_COR_DIFF1) << (channel_id * 2U)); in adc_sam_channel_setup()
110 adc->ADC_CGR &= ~(ADC_CGR_GAIN0_Msk << (channel_id * 2U)); in adc_sam_channel_setup()
121 adc->ADC_CGR |= ADC_CGR_GAIN0(1) << (channel_id * 2U); in adc_sam_channel_setup()
124 adc->ADC_CGR |= ADC_CGR_GAIN0(2) << (channel_id * 2U); in adc_sam_channel_setup()
131 adc->ADC_CGR |= ADC_CGR_GAIN0(3) << (channel_id * 2U); in adc_sam_channel_setup()
144 Adc *const adc = cfg->regs; in adc_sam_start_conversion() local
146 adc->ADC_CR = ADC_CR_START; in adc_sam_start_conversion()
[all …]
Dadc_stm32wb0.c405 static void configure_tempsensor_calib_point(ADC_TypeDef *adc, uint32_t calib_point) in configure_tempsensor_calib_point() argument
416 LL_ADC_ConfigureCalibPoint(adc, calib_point, gain, 0x0); in configure_tempsensor_calib_point()
488 static void adc_enter_idle_mode(ADC_TypeDef *adc, const struct stm32_pclken *ana_clk) in adc_enter_idle_mode() argument
494 LL_ADC_Disable(adc); in adc_enter_idle_mode()
498 LL_ADC_SMPSSyncDisable(adc); in adc_enter_idle_mode()
513 LL_ADC_DisableInternalRegulator(adc); in adc_enter_idle_mode()
526 static int adc_exit_idle_mode(ADC_TypeDef *adc, const struct stm32_pclken *ana_clk) in adc_exit_idle_mode() argument
552 LL_ADC_EnableInternalRegulator(adc); in adc_exit_idle_mode()
571 LL_ADC_SMPSSyncEnable(adc); in adc_exit_idle_mode()
575 LL_ADC_Enable(adc); in adc_exit_idle_mode()
[all …]
/Zephyr-latest/soc/atmel/sam0/common/
Dadc_fixup_sam0.h11 #define ADC_SYNC(adc) ((adc)->SYNCBUSY.reg) argument
14 #define ADC_SYNC(adc) ((adc)->STATUS.reg) argument
21 #define ADC_DIFF(adc) (inputctrl) argument
24 #define ADC_DIFF(adc) ((adc)->CTRLB.reg) argument
27 #define ADC_DIFF(adc) ((adc)->CTRLC.reg) argument
34 #define ADC_RESSEL(adc) ((adc)->CTRLB.bit.RESSEL) argument
40 #define ADC_RESSEL(adc) ((adc)->CTRLC.bit.RESSEL) argument
50 #define ADC_PRESCALER(adc) ((adc)->CTRLA.bit.PRESCALER) argument
53 #define ADC_PRESCALER(adc) ((adc)->CTRLB.bit.PRESCALER) argument
/Zephyr-latest/boards/actinius/icarus_som_dk/
Darduino_connector.dtsi38 compatible = "arduino,uno-adc";
40 io-channel-map = <0 &adc 2>, /* A0 = P0.15 = AIN2 */
41 <1 &adc 3>, /* A1 = P0.16 = AIN3 */
42 <2 &adc 4>, /* A2 = P0.17 = AIN4 */
43 <3 &adc 5>, /* A3 = P0.18 = AIN5 */
44 <4 &adc 6>, /* A4 = P0.19 = AIN6 */
45 <5 &adc 7>; /* A5 = P0.20 = AIN7 */
/Zephyr-latest/drivers/sensor/st/stm32_temp/
Dstm32_temp.c41 const struct device *adc; member
69 static inline void adc_enable_tempsensor_channel(ADC_TypeDef *adc) in adc_enable_tempsensor_channel() argument
71 const uint32_t path = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(adc)); in adc_enable_tempsensor_channel()
73 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(adc), in adc_enable_tempsensor_channel()
79 static inline void adc_disable_tempsensor_channel(ADC_TypeDef *adc) in adc_disable_tempsensor_channel() argument
81 const uint32_t path = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(adc)); in adc_disable_tempsensor_channel()
83 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(adc), in adc_disable_tempsensor_channel()
128 const uint16_t vdda_mv = adc_ref_internal(data->adc); in convert_adc_sample_to_temperature()
221 pm_device_runtime_get(data->adc); in stm32_temp_sample_fetch()
223 rc = adc_channel_setup(data->adc, &data->adc_cfg); in stm32_temp_sample_fetch()
[all …]
/Zephyr-latest/samples/drivers/adc/adc_sequence/boards/
Dnrf54l15dk_nrf54l15_cpuapp.overlay9 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 7>;
15 adc0 = &adc;
19 &adc {
Dnrf54h20dk_nrf54h20_cpuapp.overlay9 adc0 = &adc;
15 io-channels = <&adc 0>, <&adc 1>, <&adc 7>;
19 &adc {
/Zephyr-latest/samples/drivers/adc/adc_sequence/src/
Dmain.c17 static const struct device *adc = DEVICE_DT_GET(ADC_NODE); variable
50 if (!device_is_ready(adc)) {
51 printf("ADC controller device %s not ready\n", adc->name);
58 err = adc_channel_setup(adc, &channel_cfgs[i]);
64 vrefs_mv[i] = adc_ref_internal(adc);
76 err = adc_read(adc, &sequence);
86 adc->name, channel_cfgs[channel_index].channel_id,
/Zephyr-latest/drivers/sensor/st/stm32_vbat/
Dstm32_vbat.c24 const struct device *adc; member
49 pm_device_runtime_get(data->adc); in stm32_vbat_sample_fetch()
51 rc = adc_channel_setup(data->adc, &data->adc_cfg); in stm32_vbat_sample_fetch()
62 rc = adc_read(data->adc, sp); in stm32_vbat_sample_fetch()
72 pm_device_runtime_put(data->adc); in stm32_vbat_sample_fetch()
90 voltage = data->raw * adc_ref_internal(data->adc) * cfg->ratio / 0x0FFF; in stm32_vbat_channel_get()
107 if (data->adc == NULL) { in stm32_vbat_init()
112 if (!device_is_ready(data->adc)) { in stm32_vbat_init()
113 LOG_ERR("Device %s is not ready", data->adc->name); in stm32_vbat_init()
136 .adc = DEVICE_DT_GET(DT_INST_IO_CHANNELS_CTLR(inst)), \
/Zephyr-latest/tests/drivers/regulator/voltage/boards/
Dnrf52840dk_nrf52840_npm6001.overlay16 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>;
20 adc-avg-count = <10>;
24 &adc {
/Zephyr-latest/samples/drivers/adc/adc_dt/boards/
Dnrf54l15dk_nrf54l15_cpuapp.overlay9 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 7>;
13 &adc {
/Zephyr-latest/drivers/sensor/nuvoton/nuvoton_adc_cmp_npcx/
Dadc_cmp_npcx.c31 const struct device *adc; member
75 ret = adc_npcx_threshold_ctrl_set_param(config->adc, config->th_sel, in adc_cmp_npcx_init()
85 ret = adc_npcx_threshold_ctrl_set_param(config->adc, config->th_sel, in adc_cmp_npcx_init()
95 ret = adc_npcx_threshold_mv_to_thrval(config->adc, config->thr_mv, in adc_cmp_npcx_init()
101 ret = adc_npcx_threshold_ctrl_set_param(config->adc, in adc_cmp_npcx_init()
116 ret = adc_npcx_threshold_ctrl_set_param(config->adc, in adc_cmp_npcx_init()
138 ret = adc_npcx_threshold_mv_to_thrval(config->adc, value, &param.val); in adc_cmp_npcx_set_threshold()
144 ret = adc_npcx_threshold_ctrl_set_param(config->adc, in adc_cmp_npcx_set_threshold()
154 ret = adc_npcx_threshold_ctrl_set_param(config->adc, in adc_cmp_npcx_set_threshold()
190 ret = adc_npcx_threshold_ctrl_enable(config->adc, in adc_cmp_npcx_attr_set()
[all …]
/Zephyr-latest/drivers/sensor/lm35/
Dlm35.c26 const struct device *adc; member
40 return adc_read(cfg->adc, &cfg->adc_seq); in lm35_sample_fetch()
55 err = adc_raw_to_millivolts(adc_ref_internal(cfg->adc), cfg->ch_cfg.gain, in lm35_channel_get()
77 if (!device_is_ready(cfg->adc)) { in lm35_init()
82 adc_channel_setup(cfg->adc, &cfg->ch_cfg); in lm35_init()
90 .adc = DEVICE_DT_GET(DT_INST_IO_CHANNELS_CTLR(inst)), \
/Zephyr-latest/drivers/sensor/st/stm32_vref/
Dstm32_vref.c23 const struct device *adc; member
49 pm_device_runtime_get(data->adc); in stm32_vref_sample_fetch()
51 rc = adc_channel_setup(data->adc, &data->adc_cfg); in stm32_vref_sample_fetch()
65 rc = adc_read(data->adc, sp); in stm32_vref_sample_fetch()
76 pm_device_runtime_put(data->adc); in stm32_vref_sample_fetch()
136 if (!device_is_ready(data->adc)) { in stm32_vref_init()
137 LOG_ERR("Device %s is not ready", data->adc->name); in stm32_vref_init()
169 .adc = DEVICE_DT_GET(DT_INST_IO_CHANNELS_CTLR(0)),
/Zephyr-latest/dts/arm/st/u5/
Dstm32u595.dtsi64 adc2: adc@42028100 {
65 compatible = "st,stm32-adc";
77 st,adc-clock-source = "ASYNC";
78 st,adc-sequencer = "FULLY_CONFIGURABLE";
79 st,adc-oversampler = "OVERSAMPLER_EXTENDED";
86 adc1_2: adc@42028300 {
87 compatible = "st,stm32-adc";
98 st,adc-clock-source = "ASYNC";
99 st,adc-sequencer = "FULLY_CONFIGURABLE";
100 st,adc-oversampler = "OVERSAMPLER_EXTENDED";
/Zephyr-latest/tests/drivers/adc/adc_api/boards/
Dnrf54l15dk_nrf54l15_cpuapp.overlay9 io-channels = <&adc 0>, <&adc 1> , <&adc 2>;
13 &adc {
Dnrf54h20dk_nrf54h20_cpuapp.overlay9 io-channels = <&adc 0>, <&adc 1>, <&adc 2>;
13 &adc {
Dnrf54l15dk_nrf54l05_cpuapp.overlay9 io-channels = <&adc 0>, <&adc 1> , <&adc 2>;
13 &adc {
Dnrf54l15dk_nrf54l10_cpuapp.overlay9 io-channels = <&adc 0>, <&adc 1> , <&adc 2>;
13 &adc {
Dnrf9280pdk_nrf9280_cpuapp.overlay9 io-channels = <&adc 0>, <&adc 1>, <&adc 2>;
13 &adc {
/Zephyr-latest/drivers/sensor/microchip/mcp970x/
Dmcp970x.c30 struct adc_dt_spec adc; member
49 ret = adc_read_dt(&config->adc, &data->sequence); in fetch()
71 ret = adc_raw_to_millivolts_dt(&config->adc, &raw_val); in get()
105 if (!adc_is_ready_dt(&config->adc)) { in init()
110 ret = adc_channel_setup_dt(&config->adc); in init()
116 ret = adc_sequence_init_dt(&config->adc, &data->sequence); in init()
132 .adc = ADC_DT_SPEC_INST_GET(inst), \

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