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/Zephyr-latest/arch/xtensa/include/
Dxtensa_asm2_s.h110 s32i a0, a1, ___xtensa_irq_bsa_t_fcr_OFFSET
112 s32i a0, a1, ___xtensa_irq_bsa_t_fsr_OFFSET
113 ssi f0, a1, ___xtensa_irq_bsa_t_fpu0_OFFSET
114 ssi f1, a1, ___xtensa_irq_bsa_t_fpu1_OFFSET
115 ssi f2, a1, ___xtensa_irq_bsa_t_fpu2_OFFSET
116 ssi f3, a1, ___xtensa_irq_bsa_t_fpu3_OFFSET
117 ssi f4, a1, ___xtensa_irq_bsa_t_fpu4_OFFSET
118 ssi f5, a1, ___xtensa_irq_bsa_t_fpu5_OFFSET
119 ssi f6, a1, ___xtensa_irq_bsa_t_fpu6_OFFSET
120 ssi f7, a1, ___xtensa_irq_bsa_t_fpu7_OFFSET
[all …]
/Zephyr-latest/arch/xtensa/core/
Dxtensa_asm2_util.S52 mov a3, a1 /* Stash our original stack pointer */
61 addi a1, a1, -16
62 s32i a4, a1, 0
63 s32i a5, a1, 4
64 s32i a6, a1, 8
65 s32i a7, a1, 12
68 addi a1, a1, -16
69 s32i a8, a1, 0
70 s32i a9, a1, 4
71 s32i a10, a1, 8
[all …]
Duserspace.S62 s32i a1, a0, ___xtensa_irq_bsa_t_scratch_OFFSET
96 mov a1, a0
98 l32i a3, a1, ___xtensa_irq_bsa_t_pc_OFFSET
120 s32i a3, a1, ___xtensa_irq_bsa_t_pc_OFFSET
129 l32i a2, a1, 0
177 mov a3, a1
178 addi a1, a1, -4
179 s32i a3, a1, 0
181 l32i a3, a1, 4
198 addi a1, a1, 4
[all …]
Dwindow_vectors.S57 s32e a1, a5, -12 /* save a1 to call[j+1]'s stack frame */
79 l32e a1, a5, -12 /* restore a1 from call[i+1]'s stack frame */
134 l32e a0, a1, -12 /* a0 <- call[j-1]'s sp
136 s32e a1, a9, -12 /* save a1 to call[j+1]'s stack frame */
163 l32e a1, a9, -12 /* restore a1 from call[i+1]'s stack frame */
165 l32e a7, a1, -12 /* a7 <- call[i-1]'s sp
192 l32e a0, a1, -12 /* a0 <- call[j-1]'s sp
194 s32e a1, a13, -12 /* save a1 to call[j+1]'s stack frame */
225 l32e a1, a13, -12 /* restore a1 from call[i+1]'s stack frame */
227 l32e a11, a1, -12 /* a11 <- call[i-1]'s sp
Dxtensa_hifi.S26 addi a2, a1, (___xtensa_irq_bsa_t_hifi_OFFSET + XCHAL_CP1_SA_ALIGN - 1)
47 addi a2, a1, (___xtensa_irq_bsa_t_hifi_OFFSET + XCHAL_CP1_SA_ALIGN - 1)
/Zephyr-latest/soc/gd/gd32/gd32vf103/
Dentry.S18 li a1, 1
19 slli a1, a1, 29 # 0x2000 0000
20 bleu a1, a0, _start0800
21 srli a1, a1, 2 # 0x0800 0000
22 bleu a1, a0, _start0800
24 add a0, a0, a1
/Zephyr-latest/include/zephyr/arch/riscv/
Dsyscall.h45 register unsigned long a1 __asm__ ("a1") = arg2; in arch_syscall_invoke6()
54 : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (a5), in arch_syscall_invoke6()
66 register unsigned long a1 __asm__ ("a1") = arg2; in arch_syscall_invoke5()
74 : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (t0) in arch_syscall_invoke5()
84 register unsigned long a1 __asm__ ("a1") = arg2; in arch_syscall_invoke4()
91 : "r" (a1), "r" (a2), "r" (a3), "r" (t0) in arch_syscall_invoke4()
101 register unsigned long a1 __asm__ ("a1") = arg2; in arch_syscall_invoke3()
107 : "r" (a1), "r" (a2), "r" (t0) in arch_syscall_invoke3()
116 register unsigned long a1 __asm__ ("a1") = arg2; in arch_syscall_invoke2()
121 : "r" (a1), "r" (t0) in arch_syscall_invoke2()
/Zephyr-latest/tests/drivers/tee/optee/src/
Dmain.c32 typedef void (*smc_cb_t)(unsigned long a0, unsigned long a1, unsigned long a2, unsigned long a3,
41 uint32_t a1; member
54 void arm_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2, unsigned long a3, in arm_smccc_smc() argument
60 res->a1 = OPTEE_MSG_UID_1; in arm_smccc_smc()
67 res->a1 = OPTEE_SMC_SEC_CAP_DYNAMIC_SHM; in arm_smccc_smc()
71 res->a1 = 5; in arm_smccc_smc()
75 t_call.smc_cb(a0, a1, a2, a3, a4, a5, a6, a7, res); in arm_smccc_smc()
78 wait_call.smc_cb(a0, a1, a2, a3, a4, a5, a6, a7, res); in arm_smccc_smc()
81 send_call.smc_cb(a0, a1, a2, a3, a4, a5, a6, a7, res); in arm_smccc_smc()
86 void arm_smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a2, unsigned long a3, in arm_smccc_hvc() argument
[all …]
/Zephyr-latest/tests/bluetooth/controller/ctrl_sw_privacy_unit/src/
Dmain.c48 bt_addr_t a1, a2, a3, a4, a5; in helper_prpa_add() local
51 bt_addr_copy(&a1, BT_ADDR_INIT(0x12, 0x13, 0x14, 0x15, 0x16, 0x17)); in helper_prpa_add()
57 prpa_cache_add(&a1); in helper_prpa_add()
58 pos = prpa_cache_find(&a1); in helper_prpa_add()
85 pos = prpa_cache_find(&a1); in helper_prpa_add()
91 bt_addr_t a1, a2, a3, a4, a5; in helper_trpa_add() local
94 bt_addr_copy(&a1, BT_ADDR_INIT(0x12, 0x13, 0x14, 0x15, 0x16, 0x17)); in helper_trpa_add()
100 trpa_cache_add(&a1, 0); in helper_trpa_add()
101 pos = trpa_cache_find(&a1, 0); in helper_trpa_add()
128 pos = trpa_cache_find(&a1, 0); in helper_trpa_add()
/Zephyr-latest/arch/riscv/core/
Dpmp.S53 beq t1, a1, pmpaddr_done
69 addi a1, a1, RV_REGSIZE - 1
70 srli a1, a1, RV_REGSHIFT
82 beq a0, a1, pmpcfg_done
Dsemihost.c24 register void *a1 __asm__ ("a1") = args; in semihost_exec()
34 : "=r" (ret) : "r" (a0), "r" (a1) : "memory"); in semihost_exec()
Dswitch.S41 DO_CALLEE_SAVED(sr, a1)
44 sr sp, _thread_offset_to_sp(a1)
47 sr a1, ___thread_t_switch_handle_OFFSET(a1)
Dcoredump.c26 uint64_t a1; member
47 uint32_t a1;
96 arch_blk.r.a1 = esf->a1; in arch_coredump_info_dump()
Disr.S35 RV_E( op a1, __struct_arch_esf_a1_OFFSET(sp) );\
425 lr a1, __struct_arch_esf_a1_OFFSET(sp)
437 lb t1, _thread_offset_to_exception_depth(a1)
439 sb t1, _thread_offset_to_exception_depth(a1)
453 1: mv a1, sp
471 sr a2 __struct_arch_esf_csf_OFFSET(a1)
486 lr a1, __struct_arch_esf_a0_OFFSET(sp)
504 jalr ra, a1, 0
535 lr a1, __struct_arch_esf_a1_OFFSET(sp)
685 lr a1, ___cpu_t_current_OFFSET(s0)
[all …]
/Zephyr-latest/include/zephyr/arch/arm64/
Darm-smccc.h16 unsigned long a1; member
40 void arm_smccc_hvc(unsigned long a0, unsigned long a1,
53 void arm_smccc_smc(unsigned long a0, unsigned long a1,
/Zephyr-latest/tests/lib/cmsis_dsp/common/
Dtest_common.h29 #define DEFINE_TEST_VARIANT1(suite, name, variant, a1) \ argument
32 test_##name(a1); \
35 #define DEFINE_TEST_VARIANT2(suite, name, variant, a1, a2) \ argument
38 test_##name(a1, a2); \
41 #define DEFINE_TEST_VARIANT3(suite, name, variant, a1, a2, a3) \ argument
44 test_##name(a1, a2, a3); \
47 #define DEFINE_TEST_VARIANT4(suite, name, variant, a1, a2, a3, a4) \ argument
50 test_##name(a1, a2, a3, a4); \
53 #define DEFINE_TEST_VARIANT5(suite, name, variant, a1, a2, a3, a4, a5) \ argument
56 test_##name(a1, a2, a3, a4, a5); \
[all …]
/Zephyr-latest/subsys/bluetooth/crypto/
Dbt_crypto.c56 int bt_crypto_f5(const uint8_t *w, const uint8_t *n1, const uint8_t *n2, const bt_addr_le_t *a1, in bt_crypto_f5() argument
88 m[37] = a1->type; in bt_crypto_f5()
89 sys_memcpy_swap(m + 38, a1->a.val, 6); in bt_crypto_f5()
118 const uint8_t *iocap, const bt_addr_le_t *a1, const bt_addr_le_t *a2, in bt_crypto_f6() argument
130 LOG_DBG("a1 %s", bt_hex(a1, 7)); in bt_crypto_f6()
138 m[51] = a1->type; in bt_crypto_f6()
139 memcpy(m + 52, a1->a.val, 6); in bt_crypto_f6()
140 sys_memcpy_swap(m + 52, a1->a.val, 6); in bt_crypto_f6()
Dbt_crypto.h60 int bt_crypto_f5(const uint8_t *w, const uint8_t *n1, const uint8_t *n2, const bt_addr_le_t *a1,
81 const uint8_t *iocap, const bt_addr_le_t *a1, const bt_addr_le_t *a2,
/Zephyr-latest/include/zephyr/drivers/stepper/
Dstepper_trinamic.h69 uint16_t a1; member
93 COND_CODE_1(DT_PROP_EXISTS(node, a1), \
94 BUILD_ASSERT(IN_RANGE(DT_PROP(node, a1), TMC_RAMP_A1_MIN, \
139 .a1 = DT_PROP(node, a1), \
/Zephyr-latest/tests/bluetooth/bt_crypto/src/
Dtest_bt_crypto.c78 bt_addr_le_t a1 = {.type = 0x00, .a.val = {0xce, 0xbf, 0x37, 0x37, 0x12, 0x56}}; in ZTEST() local
87 bt_crypto_f5(w, n1, n2, &a1, &a2, mackey, ltk); in ZTEST()
103 bt_addr_le_t a1 = {.type = 0x00, .a.val = {0xce, 0xbf, 0x37, 0x37, 0x12, 0x56}}; in ZTEST() local
110 bt_crypto_f6(w, n1, n2, r, io_cap, &a1, &a2, res); in ZTEST()
/Zephyr-latest/include/zephyr/drivers/sip_svc/
Dsip_svc_proto.h136 unsigned long a1; member
180 unsigned long a1; member
Dsip_svc_driver.h72 unsigned long *a1, unsigned long *a2, unsigned long *a3,
271 unsigned long *a1, unsigned long *a2, unsigned long *a3,
275 unsigned long *a1, unsigned long *a2, in z_impl_sip_svc_plat_async_res_req() argument
286 __ASSERT(a1, "a1 shouldn't be NULL"); in z_impl_sip_svc_plat_async_res_req()
295 return api->sip_svc_plat_async_res_req(dev, a0, a1, a2, a3, a4, a5, a6, a7, buf, size); in z_impl_sip_svc_plat_async_res_req()
/Zephyr-latest/drivers/tee/optee/
Doptee.c35 uint32_t a1; member
44 typedef void (*smc_call_t)(unsigned long a0, unsigned long a1, unsigned long a2, unsigned long a3,
93 static void optee_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2, unsigned long a3, in optee_smccc_smc() argument
97 arm_smccc_smc(a0, a1, a2, a3, a4, a5, a6, a7, res); in optee_smccc_smc()
100 static void optee_smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a2, unsigned long a3, in optee_smccc_hvc() argument
104 arm_smccc_hvc(a0, a1, a2, a3, a4, a5, a6, a7, res); in optee_smccc_hvc()
650 param->a1, in handle_rpc_call()
652 u64_to_regs((uint64_t)k_mem_phys_addr(shm->addr), &param->a1, &param->a2); in handle_rpc_call()
655 param->a1 = 0; in handle_rpc_call()
662 shm = (struct tee_shm *)regs_to_u64(param->a1, param->a2); in handle_rpc_call()
[all …]
/Zephyr-latest/drivers/sip_svc/
Dsip_smc_intel_socfpga.c94 SMC_PLAT_PROTO_HEADER_SET_TRANS_ID(request->a1, trans_id); in intel_sip_smc_plat_update_trans_id()
118 unsigned long *a1, unsigned long *a2, unsigned long *a3, in intel_sip_smc_plat_async_res_req() argument
126 *a1 = 0; in intel_sip_smc_plat_async_res_req()
196 LOG_DBG("\tres->a1 %08lx", res->a1); in intel_sip_secure_monitor_call()
/Zephyr-latest/soc/intel/intel_adsp/cavs/
Dpower.c58 uint32_t a1; member
90 __asm__ volatile("mov %0, a1" : "=r"(core_desc[core_id].a1)); in _save_core_context()
101 __asm__ volatile("mov a1, %0" :: "r"(core_desc[core_id].a1)); in _restore_core_context()

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