Lines Matching refs:a1
110 s32i a0, a1, ___xtensa_irq_bsa_t_fcr_OFFSET
112 s32i a0, a1, ___xtensa_irq_bsa_t_fsr_OFFSET
113 ssi f0, a1, ___xtensa_irq_bsa_t_fpu0_OFFSET
114 ssi f1, a1, ___xtensa_irq_bsa_t_fpu1_OFFSET
115 ssi f2, a1, ___xtensa_irq_bsa_t_fpu2_OFFSET
116 ssi f3, a1, ___xtensa_irq_bsa_t_fpu3_OFFSET
117 ssi f4, a1, ___xtensa_irq_bsa_t_fpu4_OFFSET
118 ssi f5, a1, ___xtensa_irq_bsa_t_fpu5_OFFSET
119 ssi f6, a1, ___xtensa_irq_bsa_t_fpu6_OFFSET
120 ssi f7, a1, ___xtensa_irq_bsa_t_fpu7_OFFSET
121 ssi f8, a1, ___xtensa_irq_bsa_t_fpu8_OFFSET
122 ssi f9, a1, ___xtensa_irq_bsa_t_fpu9_OFFSET
123 ssi f10, a1, ___xtensa_irq_bsa_t_fpu10_OFFSET
124 ssi f11, a1, ___xtensa_irq_bsa_t_fpu11_OFFSET
125 ssi f12, a1, ___xtensa_irq_bsa_t_fpu12_OFFSET
126 ssi f13, a1, ___xtensa_irq_bsa_t_fpu13_OFFSET
127 ssi f14, a1, ___xtensa_irq_bsa_t_fpu14_OFFSET
128 ssi f15, a1, ___xtensa_irq_bsa_t_fpu15_OFFSET
132 l32i.n a0, a1, ___xtensa_irq_bsa_t_fcr_OFFSET
134 l32i.n a0, a1, ___xtensa_irq_bsa_t_fsr_OFFSET
136 lsi f0, a1, ___xtensa_irq_bsa_t_fpu0_OFFSET
137 lsi f1, a1, ___xtensa_irq_bsa_t_fpu1_OFFSET
138 lsi f2, a1, ___xtensa_irq_bsa_t_fpu2_OFFSET
139 lsi f3, a1, ___xtensa_irq_bsa_t_fpu3_OFFSET
140 lsi f4, a1, ___xtensa_irq_bsa_t_fpu4_OFFSET
141 lsi f5, a1, ___xtensa_irq_bsa_t_fpu5_OFFSET
142 lsi f6, a1, ___xtensa_irq_bsa_t_fpu6_OFFSET
143 lsi f7, a1, ___xtensa_irq_bsa_t_fpu7_OFFSET
144 lsi f8, a1, ___xtensa_irq_bsa_t_fpu8_OFFSET
145 lsi f9, a1, ___xtensa_irq_bsa_t_fpu9_OFFSET
146 lsi f10, a1, ___xtensa_irq_bsa_t_fpu10_OFFSET
147 lsi f11, a1, ___xtensa_irq_bsa_t_fpu11_OFFSET
148 lsi f12, a1, ___xtensa_irq_bsa_t_fpu12_OFFSET
149 lsi f13, a1, ___xtensa_irq_bsa_t_fpu13_OFFSET
150 lsi f14, a1, ___xtensa_irq_bsa_t_fpu14_OFFSET
151 lsi f15, a1, ___xtensa_irq_bsa_t_fpu15_OFFSET
168 s32i a0, a1, ___xtensa_irq_bsa_t_sar_OFFSET
171 s32i a0, a1, ___xtensa_irq_bsa_t_lbeg_OFFSET
173 s32i a0, a1, ___xtensa_irq_bsa_t_lend_OFFSET
175 s32i a0, a1, ___xtensa_irq_bsa_t_lcount_OFFSET
178 s32i a0, a1, ___xtensa_irq_bsa_t_exccause_OFFSET
181 s32i a0, a1, ___xtensa_irq_bsa_t_scompare1_OFFSET
186 s32i a0, a1, ___xtensa_irq_bsa_t_threadptr_OFFSET
357 mov a10, a1 /* pass "context handle" in 2nd frame's A2 */
358 mov a3, a1 /* stash it locally in A3 too */
362 l32i a1, a1, 0
363 l32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET
364 addi a1, a1, ___xtensa_irq_bsa_t_SIZEOF
367 mov a1, a3 /* restore original SP */
376 entry a1, 16
377 mov a1, a2
410 s32i a2, a1, ___xtensa_irq_bsa_t_scratch_OFFSET
420 l32i a2, a1, 0
506 mov a3, a1
537 beq a6, a1, _restore_\@
540 l32i a1, a1, 0
541 l32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET
542 addi a1, a1, ___xtensa_irq_bsa_t_SIZEOF
551 mov a1, a6
576 l32i a1, a1, 0
577 l32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET
578 addi a1, a1, ___xtensa_irq_bsa_t_SIZEOF
583 mov a1, a2
678 addi a1, a1, -___xtensa_irq_bsa_t_SIZEOF
679 s32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET
680 s32i a2, a1, ___xtensa_irq_bsa_t_a2_OFFSET
681 s32i a3, a1, ___xtensa_irq_bsa_t_a3_OFFSET
703 s32i a0, a1, ___xtensa_irq_bsa_t_ps_OFFSET
706 s32i a0, a1, ___xtensa_irq_bsa_t_ps_OFFSET
710 s32i a0, a1, ___xtensa_irq_bsa_t_pc_OFFSET