1 /*
2 * Copyright (c) 2022, Commonwealth Scientific and Industrial Research
3 * Organisation (CSIRO) ABN 41 687 119 230.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include <zephyr/toolchain.h>
9 #include <zephyr/arch/common/semihost.h>
10
11 /*
12 * QEMU requires that the semihosting trap instruction sequence, consisting of
13 * three uncompressed instructions, lie in the same page, and refuses to
14 * interpret the trap sequence if these instructions are placed across two
15 * different pages.
16 *
17 * The `semihost_exec` function, which occupies 12 bytes, is aligned at a
18 * 16-byte boundary to ensure that the three trap sequence instructions are
19 * never placed across two different pages.
20 */
semihost_exec(enum semihost_instr instr,void * args)21 long __aligned(16) semihost_exec(enum semihost_instr instr, void *args)
22 {
23 register unsigned long a0 __asm__ ("a0") = instr;
24 register void *a1 __asm__ ("a1") = args;
25 register long ret __asm__ ("a0");
26
27 __asm__ volatile (
28 ".option push\n\t"
29 ".option norvc\n\t"
30 "slli zero, zero, 0x1f\n\t"
31 "ebreak\n\t"
32 "srai zero, zero, 0x7\n\t"
33 ".option pop"
34 : "=r" (ret) : "r" (a0), "r" (a1) : "memory");
35
36 return ret;
37 }
38
