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Searched refs:USART3_SEL (Results 1 – 11 of 11) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32f0_clock.h47 #define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CFGR3_REG) macro
Dstm32f3_clock.h58 #define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CFGR3_REG) macro
Dstm32g4_clock.h53 #define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR_REG) macro
Dstm32g0_clock.h49 #define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR_REG) macro
Dstm32l4_clock.h54 #define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR_REG) macro
Dstm32f7_clock.h75 #define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, DCKCFGR2_REG) macro
Dstm32u5_clock.h70 #define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR1_REG) macro
Dstm32h5_clock.h71 #define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 6, CCIPR1_REG) macro
Dstm32n6_clock.h142 #define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR13_REG) macro
/Zephyr-latest/samples/boards/st/power_mgmt/serial_wakeup/boards/
Dnucleo_h563zi.overlay10 <&rcc STM32_SRC_HSI USART3_SEL(3)>;
/Zephyr-latest/boards/st/nucleo_n657x0_q/
Dnucleo_n657x0_q_common.dtsi171 <&rcc STM32_SRC_CKPER USART3_SEL(1)>;