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Searched refs:STM32_SRC_PLL3_R (Results 1 – 10 of 10) sorted by relevance

/Zephyr-latest/dts/arm/st/h7/
Dstm32h747.dtsi22 <&rcc STM32_SRC_PLL3_R NO_SEL>;
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32h7rs_clock.h36 #define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1) macro
37 #define STM32_SRC_PLL3_S (STM32_SRC_PLL3_R + 1)
Dstm32h7_clock.h33 #define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1) macro
35 #define STM32_SRC_CKPER (STM32_SRC_PLL3_R + 1)
Dstm32h5_clock.h37 #define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1) macro
39 #define STM32_SRC_CKPER (STM32_SRC_PLL3_R + 1)
Dstm32u5_clock.h38 #define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1) macro
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_h5.c140 ((src_clk == STM32_SRC_PLL3_R) && IS_ENABLED(STM32_PLL3_R_ENABLED))) { in enabled_clock()
334 case STM32_SRC_PLL3_R: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_u5.c146 ((src_clk == STM32_SRC_PLL3_R) && IS_ENABLED(STM32_PLL3_R_ENABLED))) { in enabled_clock()
349 case STM32_SRC_PLL3_R: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_h7.c377 ((src_clk == STM32_SRC_PLL3_R) && IS_ENABLED(STM32_PLL3_R_ENABLED))) {
629 case STM32_SRC_PLL3_R:
/Zephyr-latest/boards/st/stm32h750b_dk/
Dstm32h750b_dk.dts97 <&rcc STM32_SRC_PLL3_R NO_SEL>;
/Zephyr-latest/boards/witte/linum/
Dlinum.dts315 <&rcc STM32_SRC_PLL3_R NO_SEL>;