Home
last modified time | relevance | path

Searched refs:STM32_SRC_PLL2_R (Results 1 – 8 of 8) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32h7rs_clock.h31 #define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1) macro
32 #define STM32_SRC_PLL2_S (STM32_SRC_PLL2_R + 1)
Dstm32h7_clock.h30 #define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1) macro
31 #define STM32_SRC_PLL3_P (STM32_SRC_PLL2_R + 1)
Dstm32u5_clock.h35 #define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1) macro
36 #define STM32_SRC_PLL3_P (STM32_SRC_PLL2_R + 1)
Dstm32h5_clock.h34 #define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1) macro
35 #define STM32_SRC_PLL3_P (STM32_SRC_PLL2_R + 1)
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_h5.c137 ((src_clk == STM32_SRC_PLL2_R) && IS_ENABLED(STM32_PLL2_R_ENABLED)) || in enabled_clock()
315 case STM32_SRC_PLL2_R: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_u5.c143 ((src_clk == STM32_SRC_PLL2_R) && IS_ENABLED(STM32_PLL2_R_ENABLED)) || in enabled_clock()
331 case STM32_SRC_PLL2_R: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_h7.c375 ((src_clk == STM32_SRC_PLL2_R) && IS_ENABLED(STM32_PLL2_R_ENABLED)) ||
598 case STM32_SRC_PLL2_R:
/Zephyr-latest/boards/st/stm32h747i_disco/
Dstm32h747i_disco_stm32h747xx_m7.dts234 <&rcc STM32_SRC_PLL2_R SDMMC_SEL(1)>;