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Searched refs:STM32_PLL_R_ENABLED (Results 1 – 7 of 7) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_stm32f2_f4_f7.c99 #if defined(STM32_SRC_PLL_R) && STM32_PLL_R_ENABLED && defined(RCC_PLLCFGR_PLLR) in config_pll_sysclock()
Dclock_stm32_ll_wba.c58 ((src_clk == STM32_SRC_PLL1_R) && IS_ENABLED(STM32_PLL_R_ENABLED))) { in enabled_clock()
424 if (IS_ENABLED(STM32_PLL_R_ENABLED)) { in set_up_plls()
Dclock_stm32_ll_common.c212 if (!IS_ENABLED(STM32_PLL_R_ENABLED)) { in enabled_clock()
427 #if defined(STM32_SRC_PLL_R) & STM32_PLL_R_ENABLED in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_h5.c134 ((src_clk == STM32_SRC_PLL1_R) && IS_ENABLED(STM32_PLL_R_ENABLED)) || in enabled_clock()
492 if (IS_ENABLED(STM32_PLL_R_ENABLED)) { in set_up_plls()
Dclock_stm32_ll_u5.c140 ((src_clk == STM32_SRC_PLL1_R) && IS_ENABLED(STM32_PLL_R_ENABLED)) || in enabled_clock()
580 if (IS_ENABLED(STM32_PLL_R_ENABLED)) { in set_up_plls()
Dclock_stm32_ll_h7.c371 ((src_clk == STM32_SRC_PLL1_R) && IS_ENABLED(STM32_PLL_R_ENABLED)) ||
861 if (IS_ENABLED(STM32_PLL_R_ENABLED)) {
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h167 #define STM32_PLL_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_r) macro